Multi-Plane Network Switch Parallel Packet Transfer
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Solution Overview
Problem
Network switches struggle to maintain line rates when forwarding small packets due to limitations in clock speeds, which are not feasible to increase as demand for higher line rates grows.
Innovation Solution
The implementation of multiple data crossbars and multiple header planes in a network switch allows for the parallel transfer of multiple packets per clock cycle, enabling the maintenance of line rates even with small packets without increasing clock speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock speeds are increased to maintain line rates when forwarding small packets, then the line rate is improved, but device complexity and feasibility deteriorate
Solution Approach 1:
The network switch is divided into multiple independent header planes (first header plane, second header plane, etc.), each capable of independently controlling packet transfers. This segmentation allows parallel processing of multiple packets simultaneously, enabling the switch to maintain high line rates for small packets without requiring excessive clock speeds, as each header plane operates independently to handle a portion of the traffic load.
2Productivity
If multiple data crossbars are used to transfer packets in parallel, then productivity increases, but device complexity increases
Solution Approach 1:
Each header plane is designed to be multi-functional, capable of controlling transfers over multiple data crossbars. The header planes can dynamically select which data crossbar to use based on traffic conditions, making the control structure universal rather than requiring dedicated control logic for each crossbar. This reduces the overall device complexity while maintaining the ability to transfer multiple packets in parallel across multiple data crossbars.
3Productivity
If multiple header planes control parallel packet transfers, then productivity increases, but device complexity increases
Solution Approach 1:
Multiple header planes are merged into a coordinated system where they share common resources such as the data crossbars and output buffers. The header planes work in parallel but are integrated through a unified architecture that allows them to share control logic and resource allocation mechanisms. This merging approach enables high productivity through parallel packet transfers while reducing device complexity by eliminating redundant components that would exist if each header plane operated completely independently.
Data Source
AI summary
A network switch includes multiple data crossbars and multiple header planes for controlling the data crossbars. In an example implementation, a device includes: a plurality of header planes, each of the header planes including an input queue, an output queue, a request crossbar connected to the input queue and the output queue, and a grant crossbar connected to the input queue and the output queue; a receiver; and a header plane selector. The header plane selector is configured to: receive a transfer request for a packet from the receiver; select a header plane of the header planes based on a header of the packet; and queue the transfer request at the input queue of the header plane.