Multi-Plane Parity Data Management in Memory Sub-Systems
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Solution Overview
Problem
Conventional memory sub-systems require significant controller cache memory to store multi-page and multi-plane parity data, leading to excessive storage expenditure for data recovery operations, especially in systems with multiple planes.
Innovation Solution
The memory sub-system employs a parity data management component that generates and stores multi-plane parity data using a portion of the planes (N-1 planes) instead of all planes, reducing cache memory requirements by approximately 48 KB, and further optimizes by generating multi-page parity data to enable efficient data recovery with reduced cache usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-page and multi-plane parity data is stored using all planes, then data recovery capability is improved, but controller cache memory consumption increases
Solution Approach 1:
The patent extracts only the necessary portion of planes (N-1 planes) from the complete set of planes to generate parity data. This selective extraction maintains data recovery capability while eliminating redundant parity data that would require all N planes, thereby reducing controller cache memory consumption.
Solution Approach 2:
Instead of using all N planes to generate parity data (excessive action), the patent applies partial action by using only N-1 planes. This partial approach is sufficient for data recovery purposes while avoiding the unnecessary memory overhead of processing and storing parity data for all planes.
2Reliability
If parity data is generated using all planes, then data protection coverage is improved, but cache storage requirements increase by approximately 48 KB
Solution Approach 1:
The patent extracts the essential subset of planes (N-1 planes) needed for data protection, removing the redundant plane from the parity generation process. This extraction maintains adequate data protection coverage while reducing cache storage requirements by approximately 48 KB.
Solution Approach 2:
The patent changes the parameter of plane count used for parity generation from N planes to N-1 planes. This parameter modification reduces the volume of parity data that must be stored in cache, decreasing storage requirements by approximately 48 KB while preserving data protection functionality.
3Reliability
If multi-plane parity protection is implemented, then system reliability is improved, but memory resource expenditure increases
Solution Approach 1:
The patent extracts the minimal necessary set of planes (N-1 planes) from the complete multi-plane structure to generate parity data. This extraction maintains multi-plane parity protection and system reliability while reducing memory resource expenditure associated with storing and managing parity data for all N planes.
Solution Approach 2:
The patent applies partial action by using only N-1 planes instead of all N planes for parity generation. This partial approach provides sufficient multi-plane parity protection for system reliability while avoiding excessive memory resource expenditure on redundant parity data.
Data Source
AI summary
A parity generation operation based on a set of multiple planes of host data is executed to generate a set of multi-page parity data. The set of multi-page parity data is stored in a cache memory of a memory device. A data recovery operation is performed based on the set of multi-page parity data.