Multi-Plane Photonic IC Packaging for Dense Optical Routing
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Solution Overview
Problem
Current integrated circuits and memory technologies face challenges in miniaturization and power consumption, particularly in mobile devices, due to complex routing interconnections and limited space, which hinders performance and functionality enhancements.
Innovation Solution
The development of multi-dimensional integrated circuit architecture that utilizes all planes of an electronic board for semiconductor circuitry, employing monolithic multi-dimensional memory structures with tight-pitched vertical, horizontal, and angled inter-tier vias, and crossbar architectures in honeycomb or beehive shapes to reduce RC delay and increase memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional two-dimensional IC designs are used, then manufacturing and routing are simpler, but memory capacity and processing power are limited due to space constraints
Solution Approach 1:
The patent transitions from two-dimensional to three-dimensional integrated circuit architecture by stacking multiple semiconductor wafers vertically. This dimensional change enables significantly increased memory capacity and processing power while managing routing complexity through vertical interconnect structures that reduce the number of long horizontal interconnections required in 2D designs.
2Adaptability or versatility
If active elements are increased to provide more functionality, then performance improves, but space consumption increases
Solution Approach 1:
By stacking semiconductor wafers in three dimensions, the patent enables increased functionality through additional active elements without proportionally increasing the footprint area. The vertical stacking allows more transistors, memory cells, and functional blocks to be packed into the same planar space, thereby improving functionality while controlling space consumption.
3Area of stationary object
If miniaturization is pursued to save space, then component size decreases, but routing interconnections become increasingly complex
Solution Approach 1:
The 3D stacked architecture reduces routing complexity by replacing long horizontal interconnections with shorter vertical interconnects through the stacked layers. This dimensional change allows miniaturization of the footprint while managing routing complexity through the vertical dimension, where interconnections can be made more direct and shorter compared to 2D planar routing.
Solution Approach 2:
The patent introduces intermediate interconnect structures such as through-silicon vias and bump connections that mediate between different stacked layers. These intermediary elements facilitate efficient vertical routing and reduce the complexity of direct long-range interconnections, enabling miniaturization while maintaining manageable routing complexity.
4Volume of moving object
If traditional 3D integration schemes are used, then vertical stacking is achieved, but power consumption remains high due to long interconnection paths
Solution Approach 1:
The patent optimizes power consumption in 3D stacked architectures by strategically placing frequently accessed memory cells closer to processing elements in the vertical stack. This reduces the average distance data must travel vertically, thereby reducing dynamic power consumption associated with signal propagation through interconnects while maintaining the benefits of vertical integration.
Data Source
AI summary
Multi-dimensional photonic integrated circuits are provided, including a substrate having a first side and a second side, a multi-dimensional package having multi-dimensional planes, and one or more optical components connected to the first side and the second side of the substrate and on the multi-dimensional planes of the multi-dimensional package. The multi-dimensional planes include one or more horizontal sides and one or more vertical sides. One or more of the optical components are mounted on at least one of the horizontal sides of the multi-dimensional package and one or more of the optical components are mounted on at least one of the vertical sides of the multi-dimensional package. Hybrid systems of conventional multi-dimensional integrated circuits and multi-dimensional photonic integrated circuits also are provided.