Multi-Plane Read Disturb Scan Consolidation
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Solution Overview
Problem
Conventional memory sub-systems face performance degradation and increased resource utilization due to read disturb issues, leading to excessive memory management operations and power consumption, as they perform separate single-plane scans for data integrity checks across multiple memory planes.
Innovation Solution
Implementing a multi-plane scan consolidation method that identifies when read counts across multiple planes are approaching thresholds, allowing for simultaneous data integrity checks across all planes, reducing scan time and resource occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate single-plane scans are performed for data integrity checks across multiple memory planes, then data integrity can be verified, but scan time and resource utilization increase significantly
Solution Approach 1:
The patent merges multiple separate single-plane scan operations into a single consolidated multi-plane scan operation. The memory controller is configured to perform scans across multiple planes simultaneously rather than sequentially, combining what would traditionally be multiple separate scan operations into one unified operation that checks data integrity across all planes at once, thereby significantly reducing scan time and resource utilization while maintaining comprehensive data integrity verification
2Reliability
If separate single-plane scans are performed for data integrity checks, then data integrity can be verified, but memory controller occupation time increases
Solution Approach 1:
The patent combines multiple sequential scan operations into a single parallel multi-plane scan operation. By configuring the memory controller to perform scans across multiple planes simultaneously, the controller occupation time is reduced from the sum of individual plane scan times to a single consolidated scan operation, thereby increasing controller availability and system productivity while maintaining complete data integrity checking
3Reliability
If multiple single-plane scans are performed, then comprehensive data checking is achieved, but system bandwidth penalties increase
Solution Approach 1:
The patent merges multiple sequential scan operations into a single parallel multi-plane scan operation. By performing scans across multiple planes simultaneously rather than sequentially, the total bandwidth utilization is reduced from the sum of individual plane bandwidth demands to a single consolidated operation, thereby minimizing system bandwidth penalties while maintaining comprehensive data integrity verification
Data Source
AI summary
A processing device in a memory system determines that a first metric of a first memory unit on a first plane of a memory device satisfies a first threshold criterion. The processing device further determines whether a second metric of a second memory unit on a second plane of the memory device satisfies a second threshold criterion, wherein the second block is associated with the first block, and wherein the second threshold criterion is lower than the first threshold criterion. Responsive to the second metric satisfying the second threshold criterion, the processing device performs a multi-plane data integrity operation to determine a first reliability statistic for the first memory unit and a second reliability statistic for the second memory unit in parallel.