Multi-Plane Memory Architecture with Shared Slave Addresses
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Solution Overview
Problem
Existing memory devices face performance limitations due to insufficient address space on the bus, leading to increased data loading duration in power-on reset stages and reduced system performance, especially in multi-plane read operations.
Innovation Solution
Implementing a memory device architecture where internal memories of slave processors share a common bus address, allowing simultaneous data loading and separate control of each plane during asynchronous multi-plane read operations without increasing the address bus width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If each processor is assigned a unique bus address, then address space is sufficient for individual identification, but data loading duration increases during power-on reset stages
Solution Approach 1:
The patent merges the bus addresses of multiple slave processors (N-1 processors) into a single shared address, allowing them to be identified and controlled through the shared address space during power-on reset. This consolidation enables simultaneous data loading for all slave processors without requiring unique addresses for each, thereby reducing the data loading duration while maintaining system functionality.
2Adaptability or versatility
If bus address width is increased to accommodate more processors, then address space sufficiency is improved, but device complexity and routing resources are consumed
Solution Approach 1:
The shared bus address serves multiple functions: it identifies the group of slave processors, enables data loading for all slave processors simultaneously, and maintains address space sufficiency without requiring additional address bits. This multi-functional use of the shared address eliminates the need to increase bus address width, thereby preserving routing resources and reducing device complexity.
3Productivity
If simultaneous data loading is implemented for multiple processors, then power-on reset duration is reduced, but control complexity for separate plane operation increases
Solution Approach 1:
The patent segments the control functionality by assigning dedicated control signals to each slave processor for their respective planes during asynchronous multi-plane read operations. This segmentation allows simultaneous data loading through shared addresses while maintaining simple and independent control for each plane, avoiding complex control signal management.
4Productivity
If N-1 slave processors share the same bus address, then data loading efficiency is improved, but address uniqueness is compromised
Solution Approach 1:
The patent introduces a master processor as an intermediary that manages the shared bus address space. The master processor coordinates data loading operations for all slave processors sharing the same address, ensuring that data is correctly loaded into the appropriate slave processor internal memory while maintaining address identification accuracy through the master's control and arbitration.
Data Source
AI summary
Examples of the present application provide a memory device, an operation method thereof, and a memory system. The memory device includes: a memory cell array and a peripheral circuit coupled with the memory cell array, wherein the memory cell array includes N planes, and the N is a positive integer greater than 1; and the peripheral circuit includes N processors corresponding to the N planes, each of the processors is configured with a corresponding internal memory, the N processors include one master processor and N−1 slave processors, and the N−1 internal memories corresponding to the N−1 slave processors have the same bus address.