Multi-Plane NAND Write Sequencing to Cut Storage Time
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Solution Overview
Problem
Current semiconductor storage devices face challenges in efficiently managing write sequences across multiple memory planes, leading to reduced operational speed and increased storage times due to sequential execution of write commands and potential interference from crosstalk between memory planes.
Innovation Solution
The semiconductor storage device employs two sequencers to manage write sequences independently across different memory planes, allowing simultaneous execution of write operations without waiting for previous sequences to complete, and synchronizes the timing of program voltages to minimize crosstalk effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write sequences are executed sequentially across memory planes, then device complexity is reduced, but productivity decreases due to longer storage times
Solution Approach 1:
The control unit is segmented into multiple independent sequencers (first sequencer and second sequencer), each capable of independently managing write sequences for different memory planes. This segmentation enables parallel execution of write operations across multiple memory planes simultaneously, reducing overall storage time without requiring a single complex centralized controller
2Productivity
If write sequences are executed simultaneously across memory planes, then productivity increases, but crosstalk interference between memory planes worsens
Solution Approach 1:
The control unit determines and sets appropriate timing for program voltages before executing simultaneous write sequences across multiple memory planes. By preliminarily configuring the timing of program voltages for different memory planes, the system enables parallel write operations while minimizing crosstalk interference between planes through coordinated voltage application timing
3Productivity
If multiple sequencers are used to manage write sequences, then productivity increases through parallel operations, but device complexity increases
Solution Approach 1:
Each sequencer is designed with universal functionality to independently manage write sequences for any memory plane. The first sequencer can handle write sequences for first memory planes, and the second sequencer can handle write sequences for second memory planes, with both sequencers capable of performing identical write sequence management functions. This multi-functionality allows parallel operation without requiring specialized complex control logic for each sequencer
Data Source
AI summary
An operation method of a semiconductor storage device including a first memory die is provided. The first memory die includes a first memory plane including a plurality of first memory blocks, a second memory plane including a plurality of second memory blocks. The method includes starting a first write sequence with respect to one of the first memory blocks in response to a first command set designating the one of the first memory blocks and starting a second write sequence with respect to one of the second memory blocks in response to a second command set designating the one of the second memory blocks. At least part of the second write sequence is performed while the first write sequence is being performed.