Reconfigurable Multi-PLL Clock Circuit for Low Jitter Output
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Solution Overview
Problem
Conventional communication systems face challenges in minimizing clock jitter while efficiently generating clock signals with different frequencies, requiring a flexible and simple solution to ensure accuracy.
Innovation Solution
A circuit utilizing reconfigurable multi-phase-locked loops, a data selector, and a signal synthesizer to adjust and combine clock signals, enabling the generation of low-jitter clock signals or multiple frequency clock signals by synchronizing and averaging output signals from multiple phase-locked loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple phase-locked loops are used to generate clock signals with different frequencies, then frequency versatility is improved, but clock jitter increases
Solution Approach 1:
The system dynamically reconfigures the phase-locked loops based on operational requirements. When low jitter is needed, multiple PLLs are synchronized to identical frequency and phase; when frequency diversity is needed, PLLs operate at different frequencies. This dynamic adaptation resolves the contradiction between versatility and jitter performance.
Solution Approach 2:
The system changes operational parameters (frequency and phase) of the phase-locked loops based on requirements. By adjusting these parameters, the same hardware configuration can deliver either low jitter (when parameters are synchronized) or frequency versatility (when parameters are diversified), eliminating the need for separate hardware configurations.
2Reliability
If multiple phase-locked loops are used to minimize clock jitter, then jitter performance is improved, but device complexity increases
Solution Approach 1:
Multiple phase-locked loops are designed with multi-functionality: they can operate independently for frequency diversity or be synchronized for low jitter performance. The same hardware structure serves both purposes, reducing the need for separate dedicated circuits for jitter reduction and frequency generation.
Solution Approach 2:
The system merges the functions of multiple PLLs by synchronizing their output signals through a signal synthesizer. This combining approach allows the system to achieve low jitter performance through signal averaging while utilizing the same hardware resources that provide frequency versatility, thereby reducing overall device complexity.
3Measurement precision
If multiple phase-locked loops are synchronized to generate low jitter clock signals, then clock signal accuracy is improved, but configuration flexibility is reduced
Solution Approach 1:
The system implements dynamic configuration capability where the phase-locked loops can be reconfigured between synchronized mode (for high accuracy) and independent mode (for frequency versatility). This dynamic switching mechanism maintains configuration flexibility while achieving high clock signal accuracy when needed.
Data Source
AI summary
A circuit for eliminating clock jitter based on reconfigurable multi-phase-locked loops includes multiple phase-locked loops, a data selector and a signal synthesizer. In a case of generating a clock signal with low jitter, output signals of two phase-locked loops are adjusted to be the same in frequency and phase, and output signals of other phase-locked loops are adjusted to be different from each other in frequency. The data selector selects output signals, and the signal synthesizer is enabled to superimpose and then average the first and second selected output signals, so as to obtain a clock signal with jitter eliminated. In a case of generating multiple clock signals with different frequencies, output signals of the multiple phase-locked loops are adjusted to be different from each other in frequency, to obtain multiple clock signals with different frequencies through the data selector without enabling the signal synthesizer.