Multi-PLL Link Adjustment Circuit for Low-Delay Rate Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing data transmission between communications devices experiences significant delay, particularly in high real-time applications like self-driving and facial recognition, and using low-loss panels or cables to reduce this delay increases costs and is limited to specific length ranges.
Innovation Solution
A link adjustment circuit that includes a retimer with multiple phase locked loops, allowing for transparent signal transmission by configuring unused loops in advance to handle rate changes, reducing delay and bit errors through equalization adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a low-loss panel or cable is used to reduce transmission delay, then the transmission delay is reduced, but the cost increases significantly and the solution is limited to specific length ranges
Solution Approach 1:
The patent introduces a retimer as an intermediary device in the transmission path. The retimer receives signals from the transmitter, performs equalization processing to compensate for channel loss and distortion, and retransmits the equalized signals to the receiver. This intermediary approach allows the use of standard, lower-cost panels or cables while achieving low delay through active signal conditioning rather than relying solely on passive low-loss transmission media.
Solution Approach 2:
The patent employs equalization processing that dynamically adjusts transmission parameters to compensate for channel characteristics. By changing equalization parameters based on detected channel conditions, the system optimizes signal quality and reduces effective transmission delay without requiring expensive low-loss panels, thereby resolving the contradiction between transmission performance and cost.
2Loss of time
If a low-loss panel or cable is used to reduce transmission delay, then the transmission delay is reduced, but the solution is limited to specific length ranges
Solution Approach 1:
The retimer acts as an intermediary that extends the usable length range of transmission panels. By performing equalization processing, the retimer compensates for signal degradation over distance, allowing standard panels to be used beyond their native optimal length ranges. This makes the transmission system adaptable to various length requirements without being constrained by the limited support range of individual panel types.
Solution Approach 2:
The patent implements dynamic equalization that adapts to different transmission lengths and channel conditions. The equalization parameters are adjusted based on the actual channel characteristics, enabling the system to maintain low delay performance across a wide range of panel lengths. This dynamic adaptation provides versatility in supporting different length requirements while maintaining low transmission delay.
3Reliability
If traditional retimer processing is used with serial-to-parallel conversion and buffering, then signal equalization is achieved, but the transmission delay increases
Solution Approach 1:
The patent extracts and eliminates the buffering step from the traditional retimer processing chain. By using transparent transmission mode where the retimer directly processes and forwards signals without serial-to-parallel conversion and buffering operations, the system maintains signal equalization quality while removing the delay introduced by these processing steps. This extraction of unnecessary processing stages resolves the contradiction between equalization quality and transmission delay.
Solution Approach 2:
The patent implements a streamlined processing path that skips traditional retimer operations such as serial-to-parallel conversion and buffering. The retimer performs essential equalization processing and immediately forwards the equalized signals, rushing through the transmission process with minimal delay. This approach maintains the reliability of signal equalization while minimizing the time loss associated with conventional retimer architectures.
Data Source
Figure 1~2
Figure 3
Figure 4~5
AI summary
This application provides a link adjustment circuit. The link adjustment circuit comprises a link status circuit and a phase locked loop control circuit, wherein the link status circuit is configured to obtain a signal transmitted in a data channel circuit; the link status circuit is further configured to obtain link status information based on the obtained signal; the link status circuit is further configured to determine, based on the link status information, that a rate of a link needs to be changed; the phase locked loop control circuit is configured to: when the link status circuit determines that the rate of the link needs to be changed, configure an operating parameter of a target phase locked loop as an operating parameter corresponding to a changed rate, wherein the target phase locked loop is an unused phase locked loop in at least two phase locked loops; the link status circuit is further configured to detect that the link enters a rate-changing state; and the phase locked loop control circuit is further configured to switch a currently used phase locked loop to the target phase locked loop when the link status circuit detects that the link enters the rate-changing state.