Multi-PLL RF Chip Architecture for Low-Noise mmWave Beamforming

The system divides the frequency conversion process into multiple independent stages, with each RF chip performing a single frequency conversion operation. This segmentation prevents the accumulation of phase noise that would occur in a cascaded multi-conversion system, as each stage operates independently with its own PLL circuit, thereby maintaining signal quality while achieving super-high frequency generation.

A third processor acts as a clock signal distributor that supplies synchronized clock signals to multiple processors and RF chips. This intermediary ensures that all frequency conversion operations are coordinated with low phase noise correlation, preventing signal quality deterioration while enabling the multiple frequency conversions needed for mmWave generation.

The system segments the beamforming function across multiple independent RF chips, where each chip contains its own PLL circuit and performs frequency conversion independently. This segmentation allows the system to increase the number of RF chains for improved beamforming capability without creating complex inter-dependent circuits, as each chip operates as a self-contained module.

The system changes the architectural parameter from using fewer chips with complex interconnected PLL circuits to using multiple chips with simple independent PLL circuits. This parameter change enables the system to achieve high communication efficiency through increased RF chains while keeping individual chip complexity low, as each chip follows the same standardized design.