Distributed Multi-PLL Phase Locking With Phase Noise Cancellation
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Solution Overview
Problem
Existing wireless communication networks face challenges in achieving low phase noise with limited power consumption and chip area, particularly in systems with multiple transceivers, where using a single PLL leads to stringent noise performance requirements and high power consumption, while multiple PLLs risk undesired interactions due to proximity.
Innovation Solution
A distributed multi-PLL system with a primary PLL and secondary PLLs, where secondary PLLs are phase-locked to the primary PLL, using low-frequency control signals to minimize interference and maintain design modularity, and a phase noise correction loop filter to suppress oscillator coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single PLL is used to generate LO signals for multiple transceivers, then phase coherence is maintained, but the noise performance requirements become stringent and power consumption increases
Solution Approach 1:
The system divides the single PLL function into multiple distributed PLLs, where a primary PLL generates the base LO signal and secondary PLLs locally generate additional LO signals for different transceivers. This segmentation reduces the power consumption burden on a single PLL while maintaining phase coherence through controlled coupling.
Solution Approach 2:
The patent implements feedback mechanisms where secondary PLLs monitor and adjust their phase relative to the primary PLL, and where the primary PLL receives feedback about the combined output phase noise. This feedback enables the system to maintain phase coherence across multiple transceivers while distributing the power consumption load.
2Use of energy by moving object
If multiple PLLs are used to reduce power consumption per PLL, then power distribution is improved, but undesired interactions and oscillator coupling occur due to proximity
Solution Approach 1:
The patent introduces an intermediary approach where secondary PLLs are coupled to the primary PLL through controlled connections rather than operating completely independently. This intermediary coupling mechanism allows power distribution benefits while managing oscillator interactions through the structured relationship between primary and secondary PLLs.
Solution Approach 2:
The system changes operational parameters by allowing secondary PLLs to operate at slightly different phases relative to the primary PLL, and by adjusting the coupling strength between them. This parameter adjustment enables the system to achieve good phase noise performance while suppressing harmful oscillator coupling effects.
3Adaptability or versatility
If multiple PLLs are distributed across the chip, then design modularity is improved, but phase noise performance deteriorates due to interference
Solution Approach 1:
The patent segments the LO signal generation function across multiple distributed PLLs, each serving specific transceivers, thereby achieving design modularity. The primary PLL and secondary PLLs are spatially distributed but functionally coordinated to maintain overall phase noise performance.
Solution Approach 2:
The system employs feedback mechanisms where the primary PLL monitors the combined output phase noise from all PLLs and adjusts its operation accordingly. Secondary PLLs also provide feedback about their phase status, enabling the distributed system to maintain good phase noise performance despite spatial separation and potential interference.
Data Source
AI summary
An integrated, distributed, multiple Phase Locked Loop (multi-PLL) system locks the frequency and phase of multiple secondary PLLs to that of a primary PLL. The VCOs in all PLLs receive both first and second control signals. The primary PLL's primary VCO control signal is generated conventionally. using a reference periodic signal input, and is output to all secondary PLLs: hence the secondary PLLs operate at the primary PLL frequency. The primary PLL also outputs its divided periodic signal. Each secondary PLL compares its local divided periodic signal to the one received from the primary PLL (rather than to a reference signal input) in its phase locking loop. generating a secondary VCO input that locks the secondary PLL circuit phase to that of the primary PLL circuit. Selected secondary PLLs can be set to a phase offset from the primary PLL, such as by controlled DC current injected into the charge pump output. Phase noise generated by the primary PLL VCO is detected and corrected by one or more secondary PLLs in a second charge pump circuit that outputs a correction current having an inverse polarity. The correction currents are summed, and a correction loop filter generates a third VCO control signal which is provided to the second primary VCO input to correct the phase noise. Either the charge pumps scale output current (1/N) or the correction loop filter scales impedance (1/N) to account for the number (N) of secondary PLLs generating correction currents. A common mode voltage circuit may monitor selected VCO control signals of all PLLs. and maintains the common mode input level within a predetermined voltage range.