Multi-PLL Switch Matrix for Stable Clock Recovery and Fast Switching
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Solution Overview
Problem
In multi-PLL environments, existing technologies face challenges in enabling effective inter-PLL communication and stable output frequency maintenance, particularly when one PLL loses its input clock, leading to frequency drift and slow transient recovery.
Innovation Solution
Implementing a switch matrix to concurrently connect and combine frequency-correction signals from multiple PLLs, allowing each PLL to use these signals to generate a stable output clock, even when its input clock is lost, and enabling fast switching between frequencies by sharing frequency-correction information across PLLs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple PLLs operate independently without inter-PLL communication, then each PLL can be designed as a stand-alone unit with simple structure, but the system cannot achieve fast frequency switching or maintain stable output when input clock is lost
Solution Approach 1:
The patent combines frequency-correction signals from multiple independent PLLs through a switch matrix, allowing them to work together as a unified system. This merging enables the PLLs to share correction information, maintaining output stability even when individual PLLs lose their input clocks, while preserving the modular independence of each PLL unit.
Solution Approach 2:
The switch matrix acts as an intermediary that facilitates communication between independent PLLs. It selectively connects frequency-correction signals from different PLLs to their respective inputs, enabling fast frequency switching and stable output maintenance without requiring direct modification of the PLL internal structures.
2Speed
If a PLL operates independently without receiving frequency-correction signals from other PLLs, then the device structure remains simple, but the transient recovery time increases and frequency drift occurs when input clock is lost
Solution Approach 1:
The system pre-establishes multiple frequency-correction signal paths through the switch matrix before frequency switching is needed. When frequency switching is required, the switch matrix can immediately redirect the appropriate pre-available correction signals, enabling fast frequency switching without requiring complex real-time calculations or signal generation.
3Reliability
If frequency-correction signals are combined from multiple PLLs, then output frequency stability is maintained even when input clock is lost, but the device complexity increases due to switch matrix and signal combining requirements
Solution Approach 1:
The patent segments the frequency-correction signal paths, allowing each PLL to maintain its own independent correction signal while also being able to receive and utilize correction signals from other PLLs through the switch matrix. This segmentation preserves the simplicity of individual PLL units while enabling system-level redundancy and stability.
Data Source
AI summary
An electronic block includes multiple independent Phase-Locked Loops (PLLs) and a switch matrix. Each PLL has an input path and an output path. The switch matrix is operable to concurrently connect a respective signal on the output path of each PLL to the input path of another PLL. In an embodiment, each of the respective signals on the output paths is a corresponding frequency-correction signal generated by a low-pass filter (LPF) in the corresponding PLL. In an embodiment, each PLL includes a frequency-correction signal combiner to combine the frequency-correction signals received from any of the other PLLs with its own frequency-correction signal to form a combined frequency-correction signal. The combined frequency-correction signal is provided to a controlled oscillator in the PLL to generate an output clock of the PLL based on the combined frequency-correction signal. The frequency-correction signals may be analog or digital signals.