Multi-Point Reference Distribution for Faster ADC Reference Settling
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face nonlinearity issues in reference voltage due to varying current draw through capacitive digital-to-analog converters (CDACs), leading to increased settling times and reduced performance.
Innovation Solution
A multi-point reference distribution circuit is introduced, which distributes reference buffer outputs across various load circuit inputs, reducing parasitic inductance and nonlinearity caused by current variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-point reference distribution is used in ADCs, then the circuit structure is simple, but the reference voltage nonlinearity increases due to varying current draw through parasitic inductance
Solution Approach 1:
The patent divides the single reference distribution point into multiple distribution points (first reference output node and second reference output node) connected to different CDAC inputs. This segmentation reduces the current through each parasitic inductance element, thereby reducing voltage drops and nonlinearity while maintaining reasonable circuit complexity
Solution Approach 2:
The patent introduces intermediate buffer circuits (first buffer circuit and second buffer circuit) between the reference voltage source and the CDAC inputs. These buffers act as intermediaries that drive the reference voltage to multiple locations with reduced impact from parasitic inductance, improving linearity without significantly increasing overall circuit complexity
2Device complexity
If a single-point reference distribution is used in ADCs, then the circuit structure is simple, but the reference voltage settling time increases
Solution Approach 1:
The patent segments the reference distribution into multiple parallel paths with separate buffer circuits. Each buffer independently drives its associated CDAC inputs, allowing the reference voltage to settle at multiple points simultaneously rather than sequentially, thereby reducing overall settling time
Solution Approach 2:
The buffer circuits are designed to pre-drive the reference voltage to the CDAC inputs before the actual conversion process begins. This preliminary action ensures that the reference voltage is already settled at the required nodes, reducing the settling time during the critical conversion phase
3Manufacturing precision
If multi-point reference distribution is implemented, then the reference voltage linearity improves, but the circuit complexity increases
Solution Approach 1:
The patent designs the buffer circuits to perform multiple functions: they provide reference voltage driving, isolate parasitic inductance effects, and enable multi-point distribution. This multi-functionality reduces the need for additional dedicated components, thereby limiting the increase in circuit complexity while achieving improved linearity
4Loss of time
If multi-point reference distribution is implemented, then the reference voltage settling time reduces, but the circuit complexity increases
Solution Approach 1:
The patent combines the reference voltage driving function with the buffer circuits that already exist in the ADC architecture. By merging these functions into existing structures rather than adding completely separate components, the settling time is reduced while the increase in circuit complexity is minimized
Data Source
AI summary
A circuit includes an amplifier, a pre-driver circuit, and an output circuit. The amplifier has a first input, a second input, and an output. The pre-driver circuit has an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier. The output circuit includes a first transistor and a second transistor. The first transistor has a control terminal coupled to the first output of the pre-driver circuit; a first terminal, and a second terminal coupled to the third output of the pre-driver circuit. The second transistor has a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a reference terminal.