Multi-Port Cache for Emulated Shared Memory Nodes
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Solution Overview
Problem
Existing emulated shared memory (ESM) architectures face challenges in optimizing data memory access, particularly in handling multi-threaded processors and supporting strong concurrent memory access and multi-prefix operations, with existing solutions being complex, power-hungry, and costly.
Innovation Solution
A data memory node with a multi-port cache and an active memory unit connected via an interconnection network, capable of processing multioperation references and returning results to processors, while utilizing cached data for efficient execution of multi-prefix operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If distributed shared memory architecture is used, then memory access bandwidth is improved, but cache coherency maintenance becomes expensive and latency increases
Solution Approach 1:
The system segments memory access into local cache operations and remote memory operations. Local operations are handled by step caches associated with each processor, while remote operations go through the interconnection network. This segmentation reduces the burden on the global coherence protocol and allows parallel processing of memory requests.
Solution Approach 2:
The patent implements preliminary actions by pre-loading data into step caches before they are needed, and by preparing multiple memory requests in advance. The system also uses prediction mechanisms to anticipate memory access patterns and prepare data accordingly, reducing coherence maintenance overhead.
2Productivity
If step caches with high associativity are used, then concurrent memory access performance is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent applies partial action by implementing step caches with moderate associativity rather than fully associative caches. This provides sufficient performance for concurrent memory access while avoiding the excessive complexity and power consumption of fully associative designs. The system achieves acceptable productivity with reduced resource requirements.
Solution Approach 2:
Different step caches are configured with different associativity levels based on local access patterns and workload characteristics. Frequently accessed data structures have higher associativity, while less critical ones have lower associativity, optimizing the balance between performance and complexity locally.
3Ease of operation
If multi-prefix operations are implemented, then programming ease is improved, but existing memory architecture complexity increases
Solution Approach 1:
The patent implements a universal memory architecture where step caches and the interconnection network can handle multiple operation types including single operations, multi-prefix operations, and concurrent read/write operations. The same hardware infrastructure supports all these operations through configurable memory controllers and flexible request handling, avoiding the need for separate specialized hardware for each operation type.
Solution Approach 2:
The system introduces an intermediary layer in the form of step caches and memory controllers that mediate between processors and main memory. These intermediaries handle the complexity of multi-prefix operations by buffering requests, managing coherence, and coordinating access patterns, thereby simplifying the programming model while containing architectural complexity in dedicated components.
Data Source
AI summary
Data memory node (400) for ESM (Emulated Share Memory) architectures (100, 200), comprising a data memory module (402) containing data memory for storing input data therein and retrieving stored data therefrom responsive to predetermined control signals, a multi-port cache (404) for the data memory, said cache being provided with at least one read port (404A, 404B) and at least one write port (404C, 404D, 404E), said cache (404) being configured to hold recently and/or frequently used data stored in the data memory (402), and an active memory unit (406) at least functionally connected to a plurality of processors via an interconnection network (108), said active memory unit (406) being configured to operate the cache (404) upon receiving a multioperation reference (410) incorporating a memory reference to the data memory of the data memory module from a number of processors of said plurality, wherein responsive to the receipt of the multioperation reference the active memory unit (406) is configured to process the multioperation reference according to the type of the multioperation indicated in the reference, utilizing cached data in accordance with the memory reference and data provided in the multioperation reference. A method to be performed by the memory node is also presented.