Multi-port DRAM with Refresh Bypass Circuit
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Solution Overview
Problem
Dynamic random access memory (DRAM) cells require frequent refreshing due to charge leakage, which reduces system performance by suspending normal read and write operations, especially in high-speed applications where the refresh interval is shorter, leading to significant cache performance impact.
Innovation Solution
Implementing a dynamic random access memory circuit with a refresh bypass device that allows refresh operations to be performed via the write port, enabling read and write operations to proceed without interruption by hiding the refresh cycles, thereby maintaining availability of the memory array for normal operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed by suspending normal read and write operations, then the stored charges can be maintained for longer time, but the availability of the memory array for normal operations is reduced
Solution Approach 1:
The memory array is segmented into multiple independent banks (first memory bank and second memory bank). Each bank can be independently accessed and refreshed, allowing parallel operations. When one bank is being refreshed, the other bank remains available for normal read and write operations, thus maintaining system productivity while ensuring data retention.
Solution Approach 2:
The refresh operation is merged with the write operation by using the write port for both purposes. The refresh bypass device combines the refresh signal path with the write signal path, allowing the same physical infrastructure to serve dual functions. This eliminates the need for separate refresh operation time and reduces the impact on memory array availability.
2Reliability
If the refresh interval is reduced to maintain data integrity, then the retention time is improved, but the percentage of time required for refreshing increases, significantly impacting cache performance
Solution Approach 1:
The multi-port architecture enables continuous useful action by allowing normal read and write operations to proceed concurrently with refresh operations. Different ports can simultaneously access different banks, ensuring that the memory system remains productive throughout the refresh cycle rather than experiencing periodic suspensions.
Solution Approach 2:
The refresh bypass device is pre-configured to allow refresh operations to bypass the normal write operation sequence. This preliminary setup enables refresh signals to be injected without disrupting the normal write flow, effectively hiding the refresh cycles from the normal operation timeline and minimizing their impact on cache performance.
3Productivity
If a refresh bypass device is implemented to allow refresh via write port, then the availability of memory array is improved, but the device complexity increases
Solution Approach 1:
The write port is given universal functionality by enabling it to perform both normal write operations and refresh operations. The refresh bypass device acts as a multi-functional component that can route signals for both write and refresh purposes. This universality reduces the need for dedicated separate infrastructure for refresh operations, thereby limiting the increase in device complexity.
Solution Approach 2:
The refresh bypass device serves as an intermediary component that mediates between the refresh signal source and the write port. It intelligently routes refresh signals when needed while allowing normal write signals to pass through unchanged. This intermediary approach adds minimal complexity by using simple switching logic rather than requiring complete architectural redesign.
Data Source
AI summary
A dynamic random access memory circuit has at least one write bit line, at least one read bit line, a capacitive storage device, a write access device operatively coupled to the capacitive storage device and the at least one write bit line, a sense amplifier operatively coupled to the at least one read bit line and configured to generate an output signal, and a refresh bypass device operatively associated with the sense amplifier and the at least one write bit line so as to selectively pass the output signal to the at least one write bit line.