Multi-Port Memory Access for Parallel SSD Controller Channels
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Solution Overview
Problem
Concurrent access to non-volatile memory devices within a solid-state drive is limited by idle time on controller channels, leading to performance overhead and latency issues.
Innovation Solution
Implementing a multi-port memory device with separate input/output ports coupled to distinct controller channels, allowing concurrent data transfers through both ports and enabling simultaneous access to memory devices, even when one is busy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single-port memory device is used with a single controller channel, then the device structure is simple, but the channel remains idle when the device is busy, reducing productivity
Solution Approach 1:
The memory device is segmented into multiple independent ports (first port and second port), each capable of handling data transfers separately. The memory array is divided into first and second memory regions that can be accessed independently through respective ports, allowing parallel operations and eliminating channel idle time.
Solution Approach 2:
The memory device is designed with multi-functionality by implementing multiple ports that can each handle read and write operations independently. This allows the single memory device to serve multiple controller channels simultaneously, increasing channel utilization without requiring separate memory devices for each channel.
2Productivity
If concurrent access to memory devices on the same channel is prevented, then data integrity is maintained, but idle time increases and performance deteriorates
Solution Approach 1:
The patent transitions from a single-dimension access model (one channel to one memory device) to a multi-dimensional access model where multiple controller channels can simultaneously access the same memory device through different ports. This dimensional expansion allows concurrent operations without conflict.
Solution Approach 2:
The processor within the memory device acts as an intermediary that receives commands from multiple controller channels through different ports, manages the memory array access, and coordinates data transfers. This intermediary enables simultaneous access requests to be handled efficiently without compromising data integrity.
3Productivity
If multiple controller channels share a single-port memory device, then device count is reduced, but access latency increases due to sequential processing
Solution Approach 1:
The memory device segments its interface into multiple independent ports, each with dedicated command and data paths to the memory array. This segmentation allows multiple controller channels to access the memory device simultaneously through different ports, reducing access latency while maintaining a single physical memory device.
Data Source
AI summary
A multi-port memory device in communication with a controller includes a memory array for storing data provided by the controller, a first port coupled to the controller via a first controller channel, a second port coupled to the controller via a second controller channel, a processor, and a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to: enable data transfer through the first port and/or the second port in response to a first control signal received from the first controller channel and/or a second control signal received from second controller channel, decode at least one of the received first and second control signals to identify a data operation to perform, the identified data operation including a read or write operation from or to the memory array, and execute the identified data operation.