Synchronous Multi-Port Memory With Asynchronous Port Clocks
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Solution Overview
Problem
Multi-port memories face challenges in coordinating access to storage elements, leading to unpredictable access times and the need for improved synchronization, especially when interfacing with logic units operating at different frequencies.
Innovation Solution
A synchronous multi-port memory system with asynchronous ports, utilizing X-circuitry and Y-circuitry that operate independently with their own word lines and bit lines, allowing simultaneous read and write access without wait states, and processing access requests from multiple ports within one clock cycle, with each port's data being synchronized with its corresponding clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-port memory provides simultaneous access to multiple ports, then productivity is improved, but access time predictability deteriorates due to wait states and arbitration
Solution Approach 1:
The memory system is divided into two independent circuitries: X-circuitry for ports A and C, and Y-circuitry for ports B and D. Each circuitry has separate word lines, bit lines, and control logic, allowing independent operation without interference. This segmentation enables simultaneous access to multiple ports while maintaining predictable access times because each port's access path is isolated and deterministic.
Solution Approach 2:
Instead of using traditional arbitration mechanisms that introduce wait states and unpredictability, the patent inverts the approach by providing dedicated independent circuitries for different port groups. Each circuitry operates autonomously without needing to arbitrate for access, fundamentally changing how multi-port access is coordinated from competitive arbitration to parallel independent operation.
2Adaptability or versatility
If synchronous memory interfaces with asynchronous logic units, then adaptability is improved, but synchronization complexity increases
Solution Approach 1:
The memory interface is segmented into separate circuits for each port, with each port having its own control logic that independently manages its clock signal. This allows each port to interface with different asynchronous logic units without affecting other ports, distributing the synchronization complexity across independent circuits rather than requiring a single complex synchronization mechanism for all ports.
Solution Approach 2:
Each port can operate with its own clock signal having different frequencies and phases, allowing the memory to adapt to various asynchronous interfaces. The control logic for each port independently adjusts its timing parameters to match the connected logic unit's clock, enabling flexible adaptation without increasing overall system complexity.
Data Source
AI summary
A method of operating a multiport memory, which has first and second sets of word lines and bit lines for accessing a memory array, uses a first port and a second port for accesses during a first phase of a master clock and a third port and a fourth port during a second phase of the master clock. Each port has its own port clock, which clocks their own row and column addresses, that is no faster than the master clock. Assuming there is demand for it, four accesses occur for each cycle of the master clock. This has the effect of being able to be sure that a given access is complete within two cycles of the port clocks and can be operated at the rate of one access per cycle of the port clock.