Multi-Port Multi-Clock Memory Bypass for At-Speed Fault Testing
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Solution Overview
Problem
Existing testing methods for integrated circuits, particularly those with multi-port and multi-clock memories, struggle to provide comprehensive coverage for at-speed transition faults and asynchronous operations in shadow logic circuits, especially when programmable non-logic circuits operate in read and write modes.
Innovation Solution
The implementation of a multiplexer circuit in the input/output paths of memory circuits, controlled by a test bypass signal, allows for at-speed transition fault testing by enabling a bypass path that matches the timing of memory access delays, using read and write clocks to synchronize test data paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If BIST mechanisms are used for testing memory circuits, then memory testing coverage is improved, but testing coverage of surrounding digital logic circuits (shadow logic) deteriorates
Solution Approach 1:
The testing mechanism is segmented into separate functional components: BIST circuitry dedicated to memory array testing, scan chain mechanisms for shadow logic testing, and a multiplexer-based output circuit that can selectively route test data from either memory BIST or shadow logic scan chains. This segmentation allows each subsystem to be optimized independently while providing comprehensive overall coverage.
Solution Approach 2:
The output circuit is designed with multi-functionality to serve dual purposes: it can output test results from memory BIST operations and simultaneously support shadow logic testing through scan chain integration. The multiplexer enables a single output interface to handle multiple test data sources, making the testing system universally applicable to both memory and surrounding logic circuits.
2Adaptability or versatility
If scan chain testing mechanisms are used for digital logic circuits, then shadow logic testing is improved, but at-speed transition fault testing capability deteriorates
Solution Approach 1:
The testing system employs dynamic control through clock signals and multiplexer selection to adapt the test data path based on the specific test mode being executed. During at-speed transition fault testing, the system dynamically routes test patterns through the memory interface at high speeds. During shadow logic testing, it dynamically switches to scan chain mode. This dynamic reconfiguration allows the system to maintain high testing effectiveness across different test types without compromising at-speed capability.
3Adaptability or versatility
If memory circuits asynchronously operate in read and write mode, then operational flexibility is improved, but testing complexity for transition faults deteriorates
Solution Approach 1:
The multiplexer circuit serves as an intermediary element between the memory array and the output, providing a controlled interface that simplifies testing of asynchronous read/write operations. By inserting this intermediary, the system can selectively route test data from either read or write operations through a unified output path, reducing the complexity of testing asynchronous operations while maintaining operational flexibility.
Data Source
AI summary
A memory circuit includes an address port, a data input port and a data output port. An upstream shadow logic circuit is coupled to provide address data to the address port of the memory circuit and input data to the data input port of the memory circuit. A downstream shadow logic circuit is coupled to receive output data from the data output port of the memory circuit. The memory circuit includes a bypass path between the address port and the data output port. This bypass path is activated during a testing operation to pass bits of the address data (forming test data) applied by upstream shadow logic circuit from the address port to the data output port.