Multi-Port Memory Circuit With Shared Wordlines
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Solution Overview
Problem
Conventional memory circuits face challenges in achieving high memory bandwidth and simultaneous multiple read/write operations without incurring a significant circuit area penalty, as they often require larger surface areas or trade off between speed and area.
Innovation Solution
A memory circuit design incorporating a first and second wordline driver, a memory cell, a sense amplifier, and a latch, which allows for high-speed memory access and multiple simultaneous read/write operations while minimizing circuit area through the use of shared wordlines and low-swing sense amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional full-swing 8T memory cell with separate read and write wordline drivers is used, then the memory speed is relatively fast and it can support one read and one write at a time, but the circuit area is significantly increased
Solution Approach 1:
The patent combines read and write operations into a unified 10T memory cell structure with shared bitlines, allowing multiple simultaneous operations while maintaining compact area. The merged architecture integrates sense amplifiers and latch circuits that can handle both read and write functions without requiring separate dedicated circuits for each operation type.
Solution Approach 2:
The memory cell design implements multi-functional wordline drivers that can operate in different modes (read-only, write-only, or simultaneous read/write) depending on control signals. This universal driver architecture eliminates the need for separate dedicated read and write wordline drivers, reducing overall circuit area while maintaining the capability to support multiple simultaneous operations.
2Area of stationary object
If a conventional low-swing 6T memory cell with a single wordline driver is used, then the circuit area is relatively small, but the memory speed is relatively slow and it can support only one read or one write at a given time
Solution Approach 1:
The patent segments the memory access function into multiple parallel operation paths within the 10T cell structure. By dividing the bitline driving functions and using separate control mechanisms for read and write operations, the design enables simultaneous access to multiple memory locations, thereby increasing memory bandwidth without proportionally increasing area.
Solution Approach 2:
The memory cell employs dynamic control mechanisms where wordline drivers can be selectively activated or deactivated based on operation type. The circuit transitions between different operational states (read mode, write mode, simultaneous mode) through control signals, allowing flexible adaptation to different bandwidth requirements while maintaining area efficiency.
3Productivity
If a conventional low-swing 8T memory cell with shared read/write bitlines is used, then it can support two reads, or one write and one read, or two writes at a time, but the memory speed is relatively slow and the circuit area is relatively large
Solution Approach 1:
The patent changes the voltage swing parameters and timing characteristics of the bitline drivers to optimize for speed. By adjusting the drive strength and voltage levels dynamically based on operation type, the circuit achieves faster access times while maintaining the capability to support multiple simultaneous operations. The sense amplifier timing is also optimized to work with the modified bitline parameters.
Data Source
AI summary
A multi-port hybrid full-swing/low-swing memory circuit in a static random access memory (SRAM) device comprises a first wordline driver that comprises a read wordline driver, a second wordline driver that comprises either a read wordline driver or a read/write wordline driver, a memory cell coupled to the first and second wordline drivers, a sense amplifier coupled to the memory cell, and a latch coupled to the memory cell. The memory circuit is capable of achieving high-speed low-swing or low-speed full-swing operations while avoiding the need for a large circuit area on an integrated circuit.