Multi-Port Memory Clipping Circuits for Overlapping Read-Write Access
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Solution Overview
Problem
Multi-port semiconductor memory devices experience address contention during simultaneous read and write operations, leading to interference and potential data errors due to the concurrent access of multiple ports, which can cause operations to fail.
Innovation Solution
The implementation of clipping circuits that apply read blocking voltages to bit lines during overlapping operations, preventing data disturbance by ensuring bit line voltages remain above a predetermined level, thus inhibiting interference between read and write operations across different ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If simultaneous read and write operations are performed through different ports, then operational efficiency is improved, but data errors occur due to address contention and interference
Solution Approach 1:
A clipping circuit is introduced as an intermediary component between the bit line and memory cell. This circuit includes a clipping transistor that actively monitors and controls bit line voltage, preventing it from dropping below a predetermined threshold during overlapping read/write operations. The clipping circuit mediates the conflict between simultaneous port operations by blocking voltage drops that would cause data disturbance, thereby enabling high-speed concurrent operations without compromising data integrity.
2Speed
If address contention is allowed during concurrent port operations, then operational speed is improved, but interference between ports causes operation failure
Solution Approach 1:
The clipping circuit performs preliminary protective action by preemptively preventing bit line voltage from dropping to harmful levels before interference can occur. When a write operation is detected on one port, the clipping circuit proactively clamps the bit line voltage of the other port, creating a protective barrier against potential read disturbance. This preliminary anti-action allows address contention to occur without causing operation failure, thereby maintaining high operational speed while ensuring reliability.
Data Source
AI summary
An integrated circuit device includes a memory array having a multi-port memory cell (e.g., dual-port SRAM cell) therein. This multi-port memory cell includes at least first and second read/write ports, which may be provided by respective access transistors (e.g., N-type MOS transistors) that are responsive to word line signals. The first and second read/write ports are electrically coupled to the first and second bit lines, respectively. A first clipping circuit is also provided. The first clipping circuit is responsive to a first write control signal. The first clipping circuit is configured to bias the first bit line with a read blocking voltage during a first “overlapping” operation to write data from the second bit line into the multi-port memory cell concurrently with reading data from the multi-port memory cell onto the first bit line.