Multi-Port Shared Memory Controller with Doorbell Preemption
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Solution Overview
Problem
In multiprocessor systems, excessive latency occurs in memory accesses from dedicated function-specific processors due to interdependencies and inter-process communication overhead, complicating debugging and real-time operations.
Innovation Solution
Implementing a multi-port memory design with separate access ports for processors like the modem control processor, using demand paging, and employing doorbell interrupts for preemption, along with hardware-supported semaphores and shadow registers for exclusive access control, to reduce latency and enable faster switching between processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single port access model is used for shared non-volatile memory through host control processor, then device complexity is reduced, but memory access latency increases due to inter-process communication overhead
Solution Approach 1:
The patent divides the memory access path into separate dedicated ports for each processor (first processor port and second processor port), eliminating the need for all processors to share a single access port through the host control processor. This segmentation allows concurrent independent memory accesses without IPC overhead, directly reducing latency while maintaining manageable complexity through dedicated access paths.
2Device complexity
If centralized memory access through host control processor is implemented, then access control is simplified, but real-time operation efficiency decreases due to inter-dependencies
Solution Approach 1:
The patent introduces semaphore control as an intermediary mechanism that manages access to shared resources between processors. The semaphore-based access control allows processors to independently access memory through dedicated ports while maintaining coordination through the semaphore mechanism, eliminating the need for centralized control and improving real-time efficiency.
Solution Approach 2:
The patent implements dynamic access control where the host control processor can dynamically switch between first processor mode and second processor mode based on real-time needs. This dynamic mode switching enables the system to adapt to different operational requirements, allowing time-critical events to be handled by the appropriate processor without rigid centralized constraints.
3Device complexity
If shared non-volatile memory is accessed through centralized host control, then memory management is simplified, but debugging complexity increases due to inter-process dependencies
Solution Approach 1:
By segmenting the memory access architecture into dedicated ports for each processor, the patent isolates memory access paths so that each processor can be debugged independently without needing to trace complex inter-process communication. The first processor and second processor have separate access paths, making it easier to detect and measure issues in each processor's memory operations independently.
4Measurement precision
If exclusive access rights are granted to shadow registers for each processor, then access control precision is improved, but device complexity increases
Solution Approach 1:
The patent creates separate shadow registers for each processor (first shadow registers and second shadow registers) that mirror the shared register space. Each processor has its own copy of the register space it needs to access, allowing precise exclusive access control. The shadow registers act as private copies that each processor can read from and write to independently, with the actual shared registers being updated only when necessary, providing precise control without requiring complex centralized management.
Data Source
AI summary
Efficient techniques using a multi-port shared non-volatile memory are described that reduce latency in memory accesses from dedicated function specific processors, such as a modem control processor. The modem processor preempts a host processor that is accessing data from a multi-port shared non-volatile memory flash device allowing the modem processor to quickly access data in the flash device. The preemption process uses a doorbell interrupt initiated by a processor that seeks access and interrupts the processor being preempted. After preemption, the host processor may resume or restart the data access. Access control by the processors utilizes a hardware semaphore atomic control mechanism. Power control of the shared non-volatile memory modules includes at least one inactivity timer to indicate when a supply voltage to the shared non-volatile memory modules can be safely reduced or turned off. Power may be restarted by any of the processors sharing the memory, allowing fast access to the data.