Multi-port Memory with Domino Read Circuit and Double Pump Timer
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Solution Overview
Problem
Existing eight transistor (8T) two-port bitcells in AI and ML hardware applications face unbalanced read and write performance due to limited read port frequency, constrained by the write port system frequency, leading to suboptimal memory performance.
Innovation Solution
A multi-port memory circuit with a multiple bitcell single-ended read port and a write port, utilizing a domino read circuit and double pump timer circuits to generate successive read pulses in one clock cycle, enabling synchronized timing signals for balanced read-write operations across multiple read ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If domino logic is used on the eight transistor (8T) two-port bitcell to enable fast read operation, then read speed is improved, but read-write performance balance deteriorates because read port frequency can only reach approximately 1.7 times the write port system frequency
Solution Approach 1:
The patent segments the read operation into multiple independent read ports (2R or 3R configuration) within the same bitcell, allowing parallel read operations. Each read port has its own dedicated read circuitry, enabling simultaneous reads without interfering with the write port operation, thus achieving balanced read-write performance while maintaining fast read speeds.
Solution Approach 2:
The patent employs periodic clocking schemes where read operations are scheduled in specific time windows that do not conflict with write operations. The read ports operate during designated phases of the clock cycle, allowing multiple reads to be performed periodically without compromising write port frequency or read-write balance.
2Reliability
If the read port clock and write port clock are set at the same system frequency, then system synchronization is improved, but read port frequency is limited and cannot run at its highest frequency
Solution Approach 1:
The patent introduces an additional dimension of parallelism by adding multiple read ports that can operate simultaneously with the write port. This allows the read subsystem to achieve higher effective throughput by performing multiple reads in parallel during the same clock cycle, rather than being limited to a single read port operating at the base clock frequency.
Solution Approach 2:
The patent designs the bitcell and associated circuitry to support multiple functions: the same bitcell structure serves both read and write operations, while the read circuitry is designed to accommodate multiple read ports. This multi-functional design allows the system to maintain synchronization while achieving higher read throughput through parallel operations.
3Productivity
If multiple read ports are added to the eight transistor (8T) bitcell to increase read bandwidth, then data read bandwidth is improved, but circuit complexity increases
Solution Approach 1:
The patent merges multiple read ports into a unified bitcell structure, sharing common elements such as the 8T bitcell core, bitlines, and control logic. By combining multiple read functions into a single integrated structure rather than using separate independent read circuits, the patent achieves high read bandwidth while minimizing the increase in overall circuit complexity.
Data Source
AI summary
A structure includes a multi-port memory including a multiple transistor bitcell single ended read port and a write port, a read circuit which is connected to a multiple transistor bitcell circuit and is also configured to evaluate the multiple transistor bitcell single ended read port, and a timer circuit for the single ended read port and which is configured to generate two successive read pulses in one clock cycle for the multi-port memory.