Multi-Port Memory Architecture Using Single-Port Array Expansion
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Solution Overview
Problem
Current memory devices lack efficient multi-port access capabilities, leading to complexity, increased area, and higher costs due to the need for true dual-port memory arrays that cannot be accessed simultaneously by two different ports.
Innovation Solution
A memory device architecture that includes a single port memory (SPM) portion connected to multiple ports via a port expansion portion, utilizing programmable circuits and FIFO logic to enable sequential access and transform requests into ordered accesses, allowing multiple ports to access the SPM portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If true dual-port memory arrays are used to enable simultaneous access by two different ports, then multi-port access capability is improved, but device complexity and manufacturing area increase
Solution Approach 1:
The memory device is segmented into a single-port memory array and a separate port expansion portion. The port expansion portion contains control logic and multiplexing circuits that enable multiple ports to access the single-port memory array sequentially, avoiding the complexity of true dual-port arrays while achieving multi-port functionality.
Solution Approach 2:
A port expansion portion is introduced as an intermediary between multiple ports and the single-port memory array. This intermediary contains control logic that receives requests from multiple ports, arbitrates access, and transforms them into ordered sequential accesses to the memory array, enabling multi-port access without requiring complex dual-port memory structures.
2Adaptability or versatility
If true dual-port memory arrays are used to enable simultaneous access by two different ports, then multi-port access capability is improved, but manufacturing area and cost increase
Solution Approach 1:
The memory device is segmented into a single-port memory array and a separate port expansion portion. The port expansion portion contains control logic and multiplexing circuits that enable multiple ports to access the single-port memory array sequentially, avoiding the complexity of true dual-port arrays while achieving multi-port functionality.
Solution Approach 2:
Multiple port interfaces and their associated control logic are merged into a single port expansion portion that shares common memory array access paths. This consolidation allows multiple ports to share the same physical memory resources and control circuits, reducing the total area compared to having separate dual-port memory arrays.
3Device complexity
If sequential access is used to simplify device architecture, then device complexity is reduced, but productivity and data transfer efficiency may be limited
Solution Approach 1:
The port expansion portion implements dynamic access control that can adapt to different access patterns. The control logic dynamically arbitrates between multiple ports, prioritizes requests, and manages data flow to optimize throughput while maintaining sequential access to the memory array, thereby improving productivity without requiring complex dual-port structures.
Data Source
AI summary
An integrated circuit device may include a first integrated circuit (IC) portion having a memory array that stores data units as storage locations and burst access circuitry that sequentially accesses N relates storage locations within the memory array, where N>1; and a second IC portion comprising a plurality of burst access registers coupled to the burst access circuitry, each burst access register having register locations to store at least N data units, and being coupled to a corresponding port by a single data unit access path.