Multi-Port Memory Device Dynamic Mode Switching
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Solution Overview
Problem
Conventional SRAM arrays can only perform one write or read operation per clock cycle, leading to increased complexity, area size, and cost, while enhanced multiple read/write capabilities in other memory arrays also pose similar challenges due to the need for additional word lines and bit lines.
Innovation Solution
The implementation of a memory device with multiple read and write ports, along with a control input port that switches between modes to enable efficient read and write operations, allowing for pseudo dual-port functionality within a single clock cycle using additional input and output ports and optimized bit line utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple read/write ports are implemented to enhance bandwidth, then read/write capability is improved, but device complexity and area size increase
Solution Approach 1:
The patent implements dynamic mode switching between single-port and dual-port operations through a control input port that receives mode signals. The memory device can switch between first read mode, second read mode, first write mode, and second write mode, allowing flexible bandwidth enhancement only when needed rather than permanently maintaining complex dual-port circuitry.
Solution Approach 2:
The memory device is designed with multi-functional capability to operate in multiple modes using the same physical hardware. The same memory array and basic read/write circuits serve both single-port and dual-port functions, eliminating the need for separate dedicated circuits for each mode and reducing overall device complexity.
2Productivity
If multiple read/write ports are implemented to enhance bandwidth, then read/write capability is improved, but chip area size increases
Solution Approach 1:
The patent merges the functionality of two separate ports into a single integrated structure. The first read port and second read port share common memory array access paths, and similarly for write ports. This consolidation allows dual-port bandwidth capability without duplicating entire port circuits, thereby controlling chip area growth.
Solution Approach 2:
The memory device dynamically activates only the necessary ports based on mode signals. When operating in first read mode, only the first read port is active; when in second read mode, both ports are utilized. This dynamic activation reduces the effective area required at any given time compared to permanently maintaining all dual-port circuits in standby.
3Device complexity
If conventional single-port operation is used to simplify circuit, then device complexity is reduced, but read/write bandwidth is limited
Solution Approach 1:
The patent provides dynamic scalability in bandwidth capability. The memory device can operate in low-complexity single-port mode when bandwidth requirements are modest, and switch to high-bandwidth dual-port mode when performance demands increase. This dynamic adaptability allows the system to optimize between complexity and productivity based on actual operational needs.
Data Source
AI summary
A memory device includes a first memory array, a first read port, a second read port, and a control input port. The first memory array contains a plurality of memory cells arranged in an array configuration. The first read port is configured to read first data from a single memory cell during a single read cycle, and the second read port is configured to read second data from a group of memory cells controlled by a common word line. Further, the control input is configured to receive a mode signal indicating a functional mode for the memory device including a first read mode and a second read mode. When the mode signal indicates the first read mode, the first read port is used to read the first data. When the mode signal indicates the second read mode, the first read port is used to read out the first data and the second read port is used to read the second data.