Multi-port Memory Device Serial I/O Test Interface
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Solution Overview
Problem
Conventional multi-port memory devices with serial I/O interfaces face challenges in high-speed testing due to the limitations of existing test devices, leading to increased production costs and competitiveness issues.
Innovation Solution
A multi-port memory device is designed with a test interface that allows for low-speed test operations using a parallel I/O interface, enabling high-speed data communication through serial I/O pads and parallel I/O pads, and includes a test port that serializes and deserializes test signals to perform testing without requiring additional high-speed test devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a serial I/O interface is used for high-speed data communication, then data processing speed is improved, but the number of buses and manufacturing cost increase
Solution Approach 1:
The patent segments the testing function from the normal data communication function by providing a dedicated test interface. The test interface uses parallel I/O interface for low-speed testing, while the serial I/O interface is used for high-speed data communication. This segmentation allows the system to achieve high-speed performance when needed without being constrained by the complexity of high-speed test equipment.
2Measurement precision
If high-speed test devices are used to test multi-port memory devices with serial I/O interfaces, then testing accuracy is improved, but production cost increases
Solution Approach 1:
The patent introduces a test interface as an intermediary that converts high-speed serial I/O signals into low-speed parallel I/O signals for testing. This intermediary allows the use of inexpensive low-speed test equipment to accurately test the high-speed serial I/O functionality, thereby reducing production cost while maintaining testing accuracy.
Solution Approach 2:
The test interface creates a copy of the serial I/O interface functionality that operates at a lower speed. By copying the serial I/O interface and running it at low speed during testing, the patent enables the use of cheap low-speed test equipment to verify the high-speed serial I/O performance, thus reducing production cost without sacrificing measurement precision.
3Device complexity
If a single port with parallel I/O interface is used, then device complexity is reduced, but multi-media function support and concurrent operations are limited
Solution Approach 1:
The patent implements multi-functionality by providing multiple ports with different I/O interface types (serial and parallel) within a single memory device. This allows the device to support both high-speed data communication and low-speed testing, as well as concurrent operations for different media functions, thereby increasing adaptability without significantly increasing device complexity.
Data Source
AI summary
A multi-port memory device includes a plurality of serial I/O data pads; a plurality of parallel I/O data pads; a plurality of first ports for performing a serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data communication with the first ports via a plurality of first data buses; and a second port for performing a parallel I/O data communication with the external devices through the parallel I/O data pads and a serial I/O data communication with the first ports via a plurality of second data buses, during a test mode.