Multi-port Memory Device with Variable Port Speeds
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Solution Overview
Problem
In multiprocessor environments, reducing the number of components in mobile devices leads to incompatibility between transmission and reception communication speeds of processing components and memory devices, necessitating a multi-port memory device that can communicate with various processing components at different data communication speeds.
Innovation Solution
A multi-port memory device with two or more ports, each operating at a different speed, where a system clock is applied to port logic for common operation with memory banks, and a port clock is divided using a clock divider circuit to achieve desired frequencies, allowing components to communicate at different data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a single memory device is used to reduce component count, then device size is reduced, but communication speed compatibility between multiple processors and memory is lost
Solution Approach 1:
The memory device is divided into multiple independent ports, each capable of operating at different clock frequencies. This segmentation allows each processor interface to be optimized for its specific speed requirements while sharing the same physical memory device, thus reducing overall component count while maintaining speed compatibility.
Solution Approach 2:
The memory device implements dynamic clock frequency adjustment for each port independently. Each port can be configured to operate at different clock speeds matching the connected processor's requirements, enabling the single memory device to adapt to multiple processors with varying speed requirements without requiring separate memory devices for each processor.
2Adaptability or versatility
If multiple memory devices are used for each processor, then communication speed compatibility is maintained, but device size increases
Solution Approach 1:
The memory device is designed as a universal interface that can simultaneously support multiple processors with different clock frequencies. By incorporating multiple ports with independent clocking capabilities, a single memory device performs the function of what would traditionally require multiple separate memory devices, thus reducing device size while maintaining compatibility with various processor speeds.
3Adaptability or versatility
If a multi-port memory device is implemented, then communication with multiple processors is enabled, but clock synchronization complexity increases
Solution Approach 1:
The clock distribution system is segmented into independent clock paths for each port. Each port has its own clock divider circuit that independently divides the reference clock to the required frequency, eliminating the need for complex inter-port clock synchronization mechanisms while enabling multi-processor communication.
Data Source
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AI summary
A multi-port memory device having two or more ports wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock and a port clock. The system clock is applied to port logic that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.