Multi-port MRAM Array with Dual Access Transistors
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Solution Overview
Problem
Magnetic random access memory (MRAM) systems face performance limitations during read and write operations, as only one memory tunnel junction (MTJ) can be accessed at a time from a shared bit line, hindering simultaneous read and write operations from different ports.
Innovation Solution
A memory array organized into rows and columns of resistive elements, with multiple access transistors and source lines, allowing dual or triple port access to resistive elements for simultaneous reading and writing, enabling multiple devices to access the same cell simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single access transistor and shared bit line configuration is used, then device complexity is reduced, but productivity decreases because only one MTJ can be accessed at a time
Solution Approach 1:
The patent divides the memory access path into multiple independent segments by providing separate access transistors for read operations and separate access transistors for write operations. Each segment can operate independently, allowing simultaneous read and write access to different MTJ cells through shared bit lines, thereby increasing overall memory access throughput without requiring a complete duplication of the memory array structure.
2Productivity
If multiple access transistors and source lines are added for dual port access, then productivity increases by enabling simultaneous read and write operations, but device complexity increases
Solution Approach 1:
The patent implements multi-functionality by designing access transistors and bit lines that can serve multiple purposes. The same bit lines are used for both read and write operations, and access transistors are configured to handle different operation modes. This universal design allows the memory structure to achieve dual-port functionality and concurrent access capabilities without requiring completely separate dedicated paths for each operation type.
Solution Approach 2:
The patent resolves the complexity issue by transitioning from a single-plane access structure to a multi-dimensional access architecture. By adding the dimension of operational independence through separate read and write access transistors, the system enables concurrent operations along the time dimension while sharing spatial resources like bit lines, effectively increasing productivity without linearly increasing overall device complexity.
3Reliability
If MTJ release and re-acquisition protocols are implemented for sequential access, then reliability is maintained, but loss of time increases due to access sequencing requirements
Solution Approach 1:
The patent applies preliminary action by pre-configuring separate read and write access transistors that are already in place and ready for operation. This eliminates the need for dynamic release and re-acquisition protocols, as each access type has its dedicated transistor already prepared. The system can immediately initiate read or write operations without sequential switching delays, maintaining reliability through proper transistor isolation while eliminating time loss associated with access protocol sequencing.
Data Source
AI summary
A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.