Multi-port MRAM Memory with DRAM and Flash Interface Conversion
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Solution Overview
Problem
Current memory systems experience performance reduction due to frequent data transfers between DRAM and flash memory, necessitating improved interface efficiency without significant changes to existing systems.
Innovation Solution
A semiconductor memory device with multiple ports and interface circuits that convert DRAM and flash memory signals into magneto-resistive random access memory (MRAM) signals, allowing simultaneous access and data transfer through different interfaces, thereby reducing latency and system size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data are frequently transferred between DRAM and flash memory, then data storage and backup functions are achieved, but system performance is reduced
Solution Approach 1:
The patent combines DRAM and flash memory into a unified memory device with a single memory cell array that can be accessed through multiple ports. The memory cell array is divided into multiple banks, where some banks are accessible via both DRAM and flash memory interfaces simultaneously, eliminating the need for data transfer between separate memory devices and improving system performance while maintaining data storage and backup functions.
Solution Approach 2:
The patent creates a universal memory device that can function as both DRAM and flash memory through multiple interface circuits. The same memory cell array can be accessed via DRAM interface circuit for high-speed operations and via flash memory interface circuit for non-volatile storage operations, allowing the single device to perform multiple functions without data transfer overhead.
2Reliability
If separate DRAM and flash memory devices are used, then data storage and backup functions are achieved, but system size increases
Solution Approach 1:
The patent merges separate DRAM and flash memory devices into a single integrated memory device. The memory cell array is shared between DRAM and flash memory interfaces, with specific banks allocated to each interface type. This consolidation reduces the total system size while maintaining both data storage (DRAM function) and backup (flash memory function) capabilities.
3Adaptability or versatility
If multiple interface circuits are added to support both DRAM and flash memory interfaces, then compatibility with existing processors is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory cell array into multiple banks, with each bank accessible through specific interface circuits. The interface circuits are divided into DRAM interface circuit and flash memory interface circuit, each handling specific protocol conversions. This segmentation allows independent optimization of each interface while reducing the complexity of any single interface circuit compared to a fully universal interface.
Solution Approach 2:
The patent introduces interface circuits as intermediary components between the memory cell array and external processors. These interface circuits perform protocol conversion, translating DRAM or flash memory interface signals into internal memory signals. This intermediary layer maintains compatibility with existing processors while simplifying the core memory architecture.
Data Source
AI summary
A semiconductor memory device is provided which includes a first port configured to connect to a first processor and including a first interface circuit; a second port configured to connect to a second processor and including a second interface circuit; and a memory cell array including a first memory area connected to the first and second ports in common. The first memory area includes a plurality of magneto-resistive random access memory cells. The first interface circuit is configured to receive a DRAM interface signals, and the second interface circuit is configured to receive a flash memory interface signals.