Multi-port Network Interface Device Shared Processing Pipeline
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Solution Overview
Problem
High-speed network interface devices face challenges in operating at wire speeds while performing protocol offload functions, especially when the LAN speed approaches or exceeds the internal bus speed, requiring efficient use of host bus bandwidth and minimizing data latency and power consumption.
Innovation Solution
A multi-port network interface device with shared processing resources, utilizing a single transmit and receive processing pipeline, and a memory-free cut-through mode that processes data packets efficiently, reducing bus operations and data storage needs, and allowing for wire-speed throughput without dedicated external memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated hardware processing pipelines are provided for each port, then processing speed and reliability are improved, but device complexity and power consumption increase
Solution Approach 1:
The patent merges multiple port processing functions into a single shared processing pipeline. The protocol processing unit is shared across multiple ports, allowing the same hardware resources to be dynamically allocated to different ports based on current traffic needs, thereby reducing overall device complexity while maintaining processing reliability through efficient resource sharing.
Solution Approach 2:
The processing pipeline is designed with universal functionality to handle protocols for multiple ports simultaneously. The protocol processing unit can be dynamically configured to process different protocol types and can serve multiple physical ports, making the hardware resource multi-functional and adaptable to various networking requirements.
2Productivity
If more processing resources are allocated to each port, then wire-speed throughput is improved, but power consumption and device complexity increase
Solution Approach 1:
Multiple ports share a common processing pipeline and protocol processing unit, eliminating the need for separate dedicated hardware for each port. This consolidation reduces the total power consumption while maintaining wire-speed throughput capability through efficient time-multiplexed resource allocation.
Solution Approach 2:
The processing resources are dynamically allocated to different ports based on real-time traffic demands. The system can adaptively switch between ports and adjust processing capacity allocation, ensuring wire-speed throughput for active ports while keeping power consumption low by activating only the necessary processing resources at any given moment.
3Quantity of substance
If dedicated external memory is provided for each port, then data storage capacity is improved, but device complexity and cost increase
Solution Approach 1:
The patent eliminates dedicated external memory for each port and instead uses a shared memory pool that serves all ports. This unified memory architecture reduces device complexity and component count while providing sufficient data storage capacity through centralized memory management and efficient data buffering across multiple ports.
4Ease of operation
If protocol offload functions are added to free host processor resources, then host processor availability is improved, but device complexity and processing overhead increase
Solution Approach 1:
Multiple protocol offload functions (TCP/IP, UDP, IPsec, etc.) are integrated into a single shared protocol processing unit. This unified approach provides comprehensive protocol offloading capabilities to free host processor resources while avoiding the device complexity that would result from implementing separate dedicated hardware for each protocol function.
Data Source
AI summary
A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface, including at least first and second physical ports, which are coupled to send and receive data packets carrying data over a packet network. A protocol processor includes a single transmit processing pipeline and a single receive processing pipeline, which are coupled between the bus interface and the network interface so as to convey the data between both of the first and second physical ports of the network interface and the memory via the bus interface while performing protocol offload processing on the data packets.