Multi-port SDRAM Mode Controller for Shared Memory Access
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Solution Overview
Problem
Using separate SDRAMs for each compute device in computing systems increases cost, power consumption, and introduces latency due to data copying and hardware complexity from interfaces like PCIe.
Innovation Solution
A multi-port SDRAM with a first and second port, a shared first memory portion, and a mode controller that allows selective switching between modes, enabling shared access to the first memory portion between compute devices, reducing the need for multiple SDRAMs and simplifying interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate SDRAMs are used for each compute device, then each compute device has dedicated memory access, but power consumption increases and hardware complexity increases
Solution Approach 1:
The patent merges multiple SDRAMs into a single multi-port SDRAM that can serve multiple compute devices. The memory device includes multiple ports (first port, second port, etc.) that can be selectively activated, allowing different compute devices to access the same physical memory without requiring separate dedicated memory modules for each device.
Solution Approach 2:
The multi-port SDRAM is designed to perform multiple functions by serving different compute devices through different ports. The memory device can operate in various modes where the same physical memory is made accessible to different ports, enabling a single memory device to replace multiple dedicated memory devices while reducing overall system power consumption.
2Reliability
If separate SDRAMs are used for each compute device, then each compute device has dedicated memory access, but hardware complexity increases due to multiple interfaces like PCIe
Solution Approach 1:
The patent combines multiple separate memory interfaces into a single integrated multi-port memory interface. Instead of having multiple compute devices connect to separate SDRAMs through individual PCIe or other interfaces, all devices access a single multi-port SDRAM through a unified interface structure, reducing the number of separate interface components and simplifying the overall hardware architecture.
3Reliability
If separate SDRAMs are used for each compute device, then each compute device has dedicated memory access, but data copying between SDRAMs introduces latency
Solution Approach 1:
The patent merges multiple separate memory devices into a single multi-port memory device where multiple compute devices can access the same physical memory simultaneously or sequentially through different ports. This eliminates the need for data copying between separate SDRAMs, as all devices access the same unified memory space directly, thereby removing the latency associated with inter-memory data transfers.
Data Source
AI summary
Examples are disclosed that relate to a multi-port synchronous dynamic random access memory (SDRAM). One example provides a multi-port SDRAM comprising a first port, a second port, a first memory portion, and a second memory portion. At least the first memory portion is configured as shared such that the first memory portion is accessible at the first port and not the second port in a first mode, and the first memory portion is accessible at the second port and not the first port in a second mode. The multi-port SDRAM further comprises a mode controller controllable to selectively change the multi-port SDRAM between at least the first mode and the second mode.