Multi-port Shared Cache Controller for Telecommunications Systems
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Solution Overview
Problem
In communication systems with multiple clients, shared memory access leads to inefficiencies due to localized memory areas, increased power consumption, and complexity, as well as issues with data coherency and cache thrashing, especially when external memory access times are high and spatial coherency is compromised.
Innovation Solution
A centralized multi-port memory controller with a cache-based approach that allocates cache lines dynamically among clients using a modified line replacement policy (MLRU), allowing clients to access a shared coherent on-chip RAM space and maintaining a pool of free cache lines for efficient data management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a centralized multi-port memory controller with cache is used to provide direct access to clients, then access speed and system throughput are improved, but cache management complexity and power consumption increase due to multi-port access conflicts and spatial coherency loss
Solution Approach 1:
The patent segments the cache memory into client-specific regions, where each client is allocated a dedicated portion of the cache. This segmentation allows each client to access its own cache region without interfering with other clients, thereby maintaining fast access speeds while reducing cache management complexity in multi-port scenarios.
Solution Approach 2:
The patent introduces a cache controller as an intermediary between the memory controller and clients. This intermediary manages the cache regions, handles allocation, and coordinates access between multiple clients, thereby reducing the complexity of direct multi-port cache management while maintaining high access speeds.
2Loss of time
If localized memory areas are allocated inside each client for burst access, then access time is reduced to 1 clock, but power and area are wasted due to inability to share memory among multiple clients
Solution Approach 1:
The patent merges the cache memory into a shared resource that is common to all clients, rather than having separate localized memory areas. This merging allows multiple clients to share the same cache space, eliminating redundant memory structures and reducing overall power consumption while maintaining fast access times through the centralized cache controller.
3Quantity of substance
If external memory is used to reduce physical memory size and cost, then memory size requirement is reduced, but access time increases to 20-30 clocks and spatial coherency is compromised
Solution Approach 1:
The patent implements a nested memory hierarchy where a small on-chip cache memory is nested within the larger external memory system. The cache provides fast access for frequently used data (1 clock access), while the external memory provides the larger storage capacity (20-30 clock access). This nesting allows the system to maintain both small footprint and fast access for critical data.
4Productivity
If multi-port cache allocation is used without maximum limits, then cache utilization is maximized, but cache thrashing increases and system latency increases due to unlimited client access conflicts
Solution Approach 1:
The patent applies different quality characteristics to different parts of the cache management system. Each client is assigned a specific maximum cache allocation limit, creating localized control over cache usage. This local quality approach prevents any single client from monopolizing the cache, reducing cache thrashing and latency while maintaining high overall utilization through fair distribution.
Data Source
AI summary
An apparatus for use in telecommunications system comprises a cache memory shared by multiple clients and a controller for controlling the shared cache memory. A method of controlling the cache operation in a shared cache memory apparatus is also disclosed. The apparatus comprises a cache memory accessible by a plurality of clients and a controller configured to allocate cache lines of the cache memory to each client according to a line configuration. The line configuration comprises, for each client, a maximum allocation of cache lines that each client is permitted to access. The controller is configured to, in response to a memory request from one of the plurality of clients that has reached its maximum allocation of cache lines, allocate a replacement cache line to the client from cache lines already allocated to the client when no free cache lines in the cache are available.