Multi-Port SRAM Cell with Buffered Read Port for Ultra-Low Voltage
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Solution Overview
Problem
Existing SRAM cells face challenges in voltage scaling due to read and write signal margin requirements, leading to inefficiencies in layout area and the need for additional voltage conversion circuits when using different supply voltages, and traditional multi-port SRAM cells have an imbalanced number of PMOS and NMOS transistors, which complicates integration into standard cell libraries.
Innovation Solution
A multi-port SRAM cell design with a balanced number of PMOS and NMOS transistors, featuring a buffered read port and separate write port with both NMOS and PMOS pass transistors, allowing for efficient operation at ultra-low voltages without external assist circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a traditional 6T SRAM cell is used with shared read/write port, then layout area is reduced, but voltage scaling is limited due to read signal margin and write signal margin requirements
Solution Approach 1:
The patent divides the read and write operations into separate ports with dedicated transistors and bit lines. The read port uses separate transistors and bit lines that are not used for writing, allowing independent optimization of read and write paths. This segmentation enables the write port to operate at ultra-low voltages without being constrained by read signal margin requirements, thus improving voltage scaling capability while maintaining compact layout.
2Reliability
If separate transistors and bit lines are used for reading and writing, then voltage scaling is improved, but layout area increases and device complexity increases
Solution Approach 1:
The patent implements a multi-port SRAM cell that can perform both read and write operations through separate dedicated ports. The read port and write port are designed with separate transistors and bit lines, allowing each port to be optimized for its specific function. This universality approach enables the cell to support both reading and writing at ultra-low voltages simultaneously, improving voltage scaling capability while managing device complexity through functional separation.
3Ease of manufacture
If an all-NMOS 6T SRAM cell is used, then manufacturing is simplified, but layout area is wasted due to imbalance between NMOS and PMOS transistors
Solution Approach 1:
The patent introduces PMOS transistors into the SRAM cell structure to create a balanced configuration. The cell now contains both NMOS and PMOS transistors in equal numbers, creating an asymmetric balance that optimizes layout area utilization. This asymmetric approach allows the cell to fit better into standard cell libraries while maintaining manufacturing feasibility through the use of both transistor types in a balanced configuration.
4Reliability
If buffered read access ports are used, then ultra-low voltage operation is enabled, but layout area is compromised
Solution Approach 1:
The patent segments the read and write functions into separate ports with dedicated transistors and bit lines. The read port includes buffered access to enable ultra-low voltage operation, while the write port uses separate transistors that do not require buffering. This segmentation allows the cell to achieve ultra-low voltage operation without compromising layout area, as the buffered read port and unbuffered write port can be efficiently arranged within the cell structure.
Data Source
AI summary
A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.