Embedded Multi-Port SRAM Layout for Fast Differential Readout
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Solution Overview
Problem
Existing multi-port SRAM configurations in semiconductor integrated circuits, particularly those mixed with logic circuits, face limitations in the number of write and readout ports, leading to reduced readout speed in single-ended readout operations.
Innovation Solution
Incorporating three differential write and readout ports within a memory cell structure, with an N-well region at the center and P-well regions on both sides, to enhance port availability without significantly increasing the occupied area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a multi-port SRAM is configured with limited write and readout ports to reduce occupied area, then the occupied area is reduced, but the readout speed cannot achieve high-speed differential readout characteristics
Solution Approach 1:
The memory cell is divided into multiple independent port units, each capable of differential write and readout operations. By segmenting the cell structure into multiple access paths with separate bit line pairs, the invention enables simultaneous or alternating access through multiple ports without interference, thereby achieving high-speed readout while maintaining compact area.
Solution Approach 2:
Each port unit in the multi-port SRAM is designed to perform both write and readout operations through differential signaling. This multi-functional design allows each port to handle diverse operations (write, read, readout) with high speed, eliminating the need for separate dedicated write ports and readout ports, thus optimizing the area-speed tradeoff.
2Productivity
If three differential write and readout ports are incorporated into the memory cell structure, then multiple fast write and readout ports are secured, but the device complexity increases
Solution Approach 1:
The memory cell is divided into multiple independent port units, each capable of differential write and readout operations. By segmenting the cell structure into multiple access paths with separate bit line pairs, the invention enables simultaneous or alternating access through multiple ports without interference, thereby achieving high-speed readout while maintaining compact area.
Solution Approach 2:
The invention merges the write and readout functions into a unified differential port structure. Each port unit integrates both write capability (through differential write bit lines) and readout capability (through differential readout bit lines), reducing the need for separate dedicated circuits and thereby managing complexity while maximizing port availability.
3Speed
If an N-well region is arranged at the center of a cell with P-well regions on both sides, then multiple fast write and readout ports are enabled, but the manufacturing precision requirements increase
Solution Approach 1:
The invention employs distinct well region configurations tailored to specific functional requirements within the memory cell. The N-well region at the center and P-well regions on both sides create localized electrical characteristics optimized for differential signaling and high-speed operations. This local quality differentiation enables precise control of carrier behavior in each region, achieving high-speed performance while managing manufacturing tolerances through functional zoning.
Data Source
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AI summary
In a chip that processes image information or the like, a multi-port SRAM is mixed together with a logic circuit such as a digital signal processing circuit. In that case, for example, in case that the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. However, in this configuration, it is obvious that there is a problem, in that while the occupied area of an embedded SRAM is reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. The outline of the present application is that three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.