Multi-Port SRAM Layout With Stacked Metal Routing for Smaller Cells
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Solution Overview
Problem
Multi-port SRAM cells face challenges in reducing cell size due to insufficient area usage in device layer and metal interconnect structures, particularly in the deep sub-micron era, leading to inadequate routing resources and design rule violations.
Innovation Solution
The layout design of multi-port SRAM cells incorporates a two-port SRAM cell with less than seven metal zero (M0) tracks within the cell height, utilizing gate-all-around (GAA) transistors and innovative metal interconnect structures to provide sufficient routing resources while adhering to design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional metal interconnect structures are used in multi-port SRAM cells, then routing resources are sufficient, but cell area becomes excessively large
Solution Approach 1:
The patent transitions from planar 2D metal interconnect布局 to a 3D stacked architecture where multiple metal layers (M0-M6) are vertically arranged. This dimensional change allows routing resources to be distributed across multiple levels, significantly reducing the horizontal cell footprint while providing adequate routing capacity for multi-port operations
Solution Approach 2:
The patent implements a hierarchical nesting structure where lower metal layers (M0-M2) handle local bit line and word line routing within the cell, while upper metal layers (M3-M6) provide global interconnect routing. This nested arrangement allows compact local connections without interfering with global routing requirements
2Productivity
If cell size is reduced in deep sub-micron era, then production efficiency increases, but routing resources become insufficient
Solution Approach 1:
By stacking metal interconnect layers vertically (M0 through M6), the patent creates additional routing dimensions without increasing the planar cell footprint. This allows sufficient routing resources to be packed into a smaller area, enabling higher cell density and improved production efficiency while maintaining adequate routing capacity
Solution Approach 2:
The patent divides the routing function across multiple segmented metal layers, with each layer dedicated to specific routing tasks (e.g., M0-M2 for local connections, M3-M6 for global interconnects). This segmentation allows optimized routing density in each layer while maintaining overall routing sufficiency in the compact cell structure
3Area of stationary object
If multi-port SRAM cell area is reduced, then area utilization improves, but design rule violations occur
Solution Approach 1:
The patent resolves design rule violations by moving routing functions to the vertical dimension through multiple metal layers. This separates closely spaced transistor structures in the device layer from their interconnect requirements in upper metal layers, allowing compact cell layout while maintaining sufficient spacing and routing capabilities to satisfy manufacturing design rules
Data Source
AI summary
A memory cell includes a device layer including a plurality of transistors and an interconnect structure disposed over the device layer. Each of the transistors includes a gate structure extending lengthwise in a first direction. The interconnect structure includes a bottommost metal line layer electrically coupled to the transistors in the device layer. The bottommost metal line layer includes metal lines arranged in first, second, third, fourth, fifth, and sixth metal tracks in order from first to sixth along the first direction. A distance between any adjacent two of the first, second, third, fourth, fifth, and six metal tracks measured along the first direction is uniform. The first metal track includes a metal line electrically coupled to an electric ground of the memory cell. The sixth metal track includes a metal line electrically coupled to a power supply of the memory cell.