Multi-ported Nonvolatile Memory with Bank Allocation
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Solution Overview
Problem
Conventional nonvolatile memory (NVM) devices have limited read data rates due to their serial data interfaces, which restrict overall data access speed.
Innovation Solution
A nonvolatile memory device with multiple banks that can be accessed via heterogeneous ports, including a parallel DDR interface for high data throughput and a serial SPI interface, allowing for simultaneous access to different banks using custom commands that enhance read operations beyond standard LPDDR4 capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a serial data interface is used in conventional NVM devices, then the device complexity is reduced, but the read data rate is limited
Solution Approach 1:
The memory device is divided into multiple banks (first bank, second bank, etc.) that can be independently accessed. This segmentation allows parallel read operations across different banks, thereby increasing the overall read data rate while maintaining manageable interface complexity through organized memory architecture
Solution Approach 2:
The patent transitions from a single-interface serial architecture to a multi-interface parallel architecture by adding both serial and parallel ports. This dimensional change in the interface architecture enables simultaneous data access through multiple pathways, dramatically improving read data rate without overwhelming the control logic
2Productivity
If multiple heterogeneous ports are added to enable parallel access, then data throughput increases, but device complexity increases
Solution Approach 1:
The memory device incorporates multiple ports (serial port and parallel port) that can access different banks, creating a universal interface architecture. This multi-functionality allows the same memory device to serve different application requirements - high-speed parallel access when needed, or low-power serial access when sufficient, thereby increasing data throughput while managing complexity through flexible multi-purpose design
Solution Approach 2:
The system dynamically allocates bank access rights between serial and parallel ports based on operational needs. The dynamic nature of the port allocation allows the system to optimize between speed and power consumption in real-time, increasing effective data throughput while keeping the control architecture manageable through adaptive resource management
3Productivity
If custom commands are implemented beyond standard LPDDR4, then read operations are enhanced, but ease of operation decreases
Solution Approach 1:
The patent introduces a controller that acts as an intermediary between the standard LPDDR4 interface and the custom extended commands. This mediator translates standard interface operations into optimized bank-specific commands, enhancing read operation efficiency while maintaining compatibility with standard interfaces and easing the operational burden on external systems
Data Source
AI summary
A memory device that includes a first port and a second port. The first port includes a first clock input, at least one first command address input, and at least one data input or output configured to transfer data in relation to the memory device. The second port includes a second clock input and at least one command, address, and data input/output (I/O) configured to receive command and address information from, and to transfer data in relation to the memory device. The memory device also includes a plurality of memory banks, in which two different memory banks may be accessed respectively by the first and the second ports concurrently. Other embodiments of the memory device and related methods and systems are also disclosed.