Multi-Precision Matrix Arithmetic Circuit With Shared Exponents
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Solution Overview
Problem
Existing arithmetic devices face challenges in performing large-scale matrix operations with multiple levels of precision due to circuit scale limitations and increased power consumption, particularly when handling floating-point number data.
Innovation Solution
The arithmetic device employs a configuration with multiply-add circuits and correction value generation circuits to perform matrix operations of floating-point number data with multiple levels of precision, using shared exponents and correction values to optimize circuit scale and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple matrix operation circuits for different precisions are mounted on a processor chip, then the arithmetic performance for multiple precision operations is improved, but the circuit scale increases and becomes difficult to implement within chip restrictions
Solution Approach 1:
The patent implements a universal matrix operation circuit that can handle multiple precision formats (half precision, single precision, double precision) through a single circuit design. The circuit uses configurable multiplier precision and shared exponent handling to perform different precision operations without requiring separate dedicated circuits for each precision level, thereby reducing overall circuit scale while maintaining arithmetic performance across multiple precision requirements
Solution Approach 2:
The patent changes the operational parameters of the matrix operation circuit dynamically based on the input data precision. The circuit adjusts its internal precision settings and exponent handling modes to match the required operation precision, allowing a single circuit to adaptively perform half precision, single precision, and double precision operations without physical reconfiguration or multiple fixed-precision circuits
2Productivity
If multiple matrix operation circuits for different precisions are mounted on a processor chip, then the arithmetic performance for multiple precision operations is improved, but the power consumption increases
Solution Approach 1:
The universal matrix operation circuit eliminates the need for multiple dedicated circuits by implementing a single circuit that can operate at different precision levels. This reduces the total number of active circuit components, thereby reducing overall power consumption while still providing arithmetic performance for half precision, single precision, and double precision operations through configurable operational modes
Solution Approach 2:
The circuit implements dynamic precision adjustment where the operational precision is changed based on the input data requirements rather than being fixed. This allows the circuit to operate at the minimum necessary precision for each task, optimizing power consumption by avoiding unnecessary high-precision operations when lower precision suffices, while maintaining the capability to switch between precision levels as needed
3Device complexity
If block floating-point number format is used to share exponents, then the circuit scale is reduced, but errors may occur due to incorrect correction value generation
Solution Approach 1:
The patent implements feedback mechanisms in the correction value generation process where the circuit monitors the input data characteristics and adjusts the correction values accordingly. The exponent sharing mechanism includes feedback loops that detect potential accuracy issues and generate appropriate correction values to maintain calculation precision, thereby preventing errors while still benefiting from the reduced circuit scale of block floating-point representation
Solution Approach 2:
The circuit performs preliminary analysis of the input data range and precision requirements before executing the matrix operation. Based on this preliminary assessment, the circuit pre-calculates and prepares the appropriate correction values for the block floating-point format, ensuring that accurate correction values are ready before the actual computation begins, thus preventing errors while maintaining compact circuit design
Data Source
AI summary
An arithmetic device includes a plurality of multiply-add circuits, each of which includes a plurality of multipliers and a first adder, each of the plurality of multipliers being configured to multiply a data pair of significands of floating-point number data, and the first adder being configured to add results of the multiplication by the plurality of multipliers and a correction value; and an addition circuit configured to add operation results output from the plurality of multiply-add circuits and output a result of the addition as a matrix multiplication result of significand data of any of a plurality of types of floating-point number formats.