Multi-Priority PLD Configuration via Simulated Annealing
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Solution Overview
Problem
Modern programmable logic devices (PLDs) face challenges in balancing routability and performance to achieve maximum achievable frequency (Fmax) due to the complexity of the place-and-route process, which often prioritizes routability over design speed, leading to suboptimal configurations.
Innovation Solution
A computer-implemented method for configuring PLDs that introduces three priority categories: routing priority, timing priority, and timing criticality, using simulated annealing to evaluate and optimize logical resource swaps based on cost values, prioritizing timing-critical connections to enhance Fmax.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional place-and-route tools prioritize routability over timing, then routing connections can be established more easily, but the maximum frequency of operation (Fmax) is reduced
Solution Approach 1:
The patent applies local quality by introducing multi-priority categories (routing priority, timing priority, timing criticality) that allow different regions and connections within the PLD to be treated differently. Timing-critical connections receive higher priority and more aggressive optimization, while less critical connections maintain standard routing, thus improving Fmax without compromising overall routability.
Solution Approach 2:
The patent changes the parameter of connection priority from a single uniform value to a multi-level hierarchy (routing priority, timing priority, timing criticality). This parameter transformation enables the place-and-route tool to differentiate between various connections and apply optimized placement and routing strategies specifically to timing-critical paths, thereby increasing Fmax while maintaining routability.
2Quantity of substance
If more logical resources are added to increase PLD capacity, then the device can implement more complex designs, but the place-and-route complexity increases making it harder to achieve optimal Fmax
Solution Approach 1:
The patent segments the place-and-route optimization process into multiple priority levels and phases. By dividing connections into routing priority, timing priority, and timing criticality categories, the tool can systematically handle complex PLDs with millions of logic gates through hierarchical optimization, making the complex routing problem more manageable and solvable.
Solution Approach 2:
The patent performs preliminary classification of connections into priority categories before the actual place-and-route optimization. This preliminary action allows the system to pre-identify timing-critical connections that require special attention, enabling more efficient optimization of large-scale PLDs by focusing computational resources on the most important connections first.
Data Source
AI summary
In one embodiment of the invention, a computer-implemented method of configuring a programmable logic device (PLD) includes placing logical functions within logical resources of the PLD to implement a desired netlist; swapping the logical function of at least one logical resource with the logical function of at least one other logical resource within the PLD; and evaluating whether to accept or reject the swap using a simulated annealing process that calculates at least three cost function values based upon routing priority groups, timing priority groups, and a timing critical group.