Multi-Processor Cluster Transaction Routing via Protocol Engines

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Solution Overview

Problem

Multi-processor systems with point-to-point communication infrastructure are limited by a fixed node ID address space, leading to a restricted number of interconnected nodes and a single level of address space mapping, which also restricts processing throughput due to the capacity of the protocol engine.

Innovation Solution

Implementing multiple protocol engines in each cluster to process transactions and using a hierarchical mapping mechanism that allows interconnection of multiple clusters, enabling a shared memory address space and increased processing throughput by mapping transaction packets based on destination information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If a point-to-point communication infrastructure with fixed node ID address space is used, then the system achieves increased information transmission capacity, but the number of interconnected nodes is limited

Engineering Contradiction:
Improveinformation transmission capacityVSAvoidnumber of interconnected nodes
Core Design Contradiction:
PowerVSQuantity of substance

Solution Approach 1:

The system is divided into multiple processor clusters, each with its own interconnection controller and protocol engines. This segmentation allows each cluster to operate independently with its own node ID space, enabling the overall system to scale beyond the fixed address space limitation of a single cluster while maintaining high transmission capacity within each cluster.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical address mapping mechanism that adds a cluster-level dimension to the traditional flat node ID address space. By mapping global addresses to cluster addresses and then to node addresses, the system extends the addressable node space from a single fixed level to a multi-level hierarchy, enabling connection of multiple clusters without increasing the base node ID space.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If a flat address space mapping is used, then the system structure is simple, but only a single level of mapping is allowed

Engineering Contradiction:
Improveaddress mapping structureVSAvoidlevels of address space mapping
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent transforms the flat single-level address mapping into a multi-level hierarchical mapping structure. The global address space is divided into cluster address spaces, which are further divided into node address spaces. This dimensional transformation allows the system to support multiple levels of mapping while maintaining manageable complexity at each level through standardized mapping mechanisms.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The address mapping structure implements a nested hierarchy where global addresses contain cluster address information, which in turn contain node address information. Each level of the hierarchy is nested within the previous level, allowing the system to maintain a structured organization of multiple mapping levels while enabling efficient address translation through staged lookup processes.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Device complexity

If a single protocol engine is used to process transactions, then the system structure is simple, but the processing throughput is limited

Engineering Contradiction:
Improveprotocol engine configurationVSAvoidtransaction processing throughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The interconnection controller is divided into multiple protocol engines, each capable of independently processing transactions. This segmentation of the protocol processing function allows parallel handling of multiple transactions simultaneously, significantly increasing throughput. Each protocol engine operates as an independent processing unit, eliminating the bottleneck of a single sequential processor.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple protocol engines are combined within a single interconnection controller, creating a unified controller that leverages the collective processing power of all engines. The engines share common resources such as the crossbar switch and memory interfaces while maintaining independent transaction processing capabilities, achieving both high throughput and resource efficiency.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8185602B2Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
Publication Date: 2012.05.22 SANMINA CORP
  • US8185602B2 patent drawing
  • US8185602B2 patent drawing
  • US8185602B2 patent drawing

AI summary

A multi-processor computer system is described in which transaction processing in each cluster of processors is distributed among multiple protocol engines. Each cluster includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller in each cluster comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.