Multi-Processor Debugging via Ring Bus and Shared Core

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Solution Overview

Problem

As the number of processor cores increases, existing multi-processor systems face a challenge in preventing the overall size of the processor from growing, which in turn affects manufacturing costs and efficiency.

Innovation Solution

A multi-processor system is designed with a debugging control unit connected to a single debugging core, allowing it to refer to and update register information across multiple cores through a ring bus configuration, enabling debugging without each core needing its own debugging function, thus maintaining a smaller processor size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a debugging function unit is provided for each processor core, then debugging capability is improved, but the processor size increases

Engineering Contradiction:
Improvedebugging capabilityVSAvoidprocessor size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

A single debugging control unit is designed to serve multiple processor cores through a ring bus interface. The debugging control unit can selectively debug any core in the ring by receiving core identification information and routing debug signals accordingly, making one debugging unit universal across all cores rather than requiring dedicated debugging units for each core.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The ring bus serves as an intermediary communication path between the debugging control unit and multiple processor cores. Debug signals and data are transmitted through the ring bus structure, allowing the debugging control unit to access any core without direct point-to-point connections, thereby reducing the overall system complexity and size.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Power

If the number of processor cores is increased, then processing power is improved, but the processor size increases

Engineering Contradiction:
Improveprocessing powerVSAvoidprocessor size
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

The processor is segmented into multiple independent cores that can be selectively activated and debugged. The ring bus architecture segments the communication path into discrete segments between adjacent cores, allowing for modular expansion without requiring a complete redesign of the debugging infrastructure for each additional core.

Inventive Principle:
Principle #1Segmentation

3Measurement precision

If a debugging I/F is provided for each processor, then debugging precision is improved, but device complexity increases

Engineering Contradiction:
Improvedebugging precisionVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The debugging control unit implements a universal debugging interface that can identify and communicate with any core in the ring through core identification information. This single multi-functional interface replaces multiple dedicated interfaces, reducing device complexity while maintaining the ability to precisely debug any individual core.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP3327573B1Multi-processor and multi-processor system
Publication Date: 2023.09.06 RENESAS ELECTRONICS CORP
  • EP3327573B1 patent drawingFigure 1
  • EP3327573B1 patent drawingFigure 2
  • EP3327573B1 patent drawingFigure 3

AI summary

The size of a multi-processor is prevented from increasing even when the number of processor cores is increased. The multi-processor includes a plurality of cores and a debugging control unit. At least one of the plurality of cores is a debugging core, the debugging core being connected to the debugging control unit so that the debugging control unit can refer to and update register information in the debugging core. The debugging control unit transfers register information in a first core to the debugging core, the first core being one of the plurality of cores and being a core to be debugged. The debugging core debugs a program by using the transferred register information, the program being to be executed in the first core.