Multi-Processor Device With Independent Buses For Different Architectures
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Solution Overview
Problem
Multi-processor devices with processors of different architectures face performance degradation due to bus contention, cache coherency issues, and the need for separate operating systems, especially when high-speed processors are impaired by low-speed processors and when multiple processors share a single bus.
Innovation Solution
Providing independent buses and external bus interfaces for each group of processors of different architectures on a single semiconductor chip, allowing each group to operate independently and reducing bus contention, thereby enabling high-performance multi-processor systems with low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple processors of different architectures are coupled to a single bus, then device complexity is reduced, but processing speed deteriorates due to bus contention between high-speed and low-speed processors
Solution Approach 1:
The patent divides the single bus system into multiple independent buses (first bus and second bus), each dedicated to specific processor groups. This segmentation eliminates bus contention between processors of different speeds while maintaining manageable system complexity through organized bus assignments.
2Adaptability or versatility
If multiple local buses are coupled together with a bridge, then processor connectivity is improved, but bus access time increases due to single bus master bottleneck
Solution Approach 1:
The patent eliminates the single bus master bottleneck by segmenting the bus architecture into multiple independent buses, each with its own master capability. This allows parallel bus operations and eliminates the sequential access bottleneck of a single bus master while maintaining comprehensive processor connectivity.
3Productivity
If a single bus is shared by multiple processor groups, then external bus interface utilization is reduced, but device complexity is lowered
Solution Approach 1:
The patent segments the external bus interface resources by providing separate external bus interfaces for different processor groups. This segmentation enables each processor group to independently access external resources, maximizing external bus interface utilization while organizing complexity through dedicated interface assignments.
Data Source
AI summary
The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.