Multi-Processor Peripheral Connectivity for Memory Latency

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Solution Overview

Problem

Multi-processor computing devices face performance degradation due to non-uniform memory access times and latency issues when peripheral components access memory locations across different hardware processors, leading to inefficient data transfer and application performance.

Innovation Solution

A peripheral computing component is electrically connected to each hardware processor, allowing local memory access via distinct electrical connections, reducing remote memory access latency and increasing throughput by using the PCIe standard for point-to-point serial communication, and enabling seamless thread migration between processors without interrupting network connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a peripheral computing component is electrically connected to only one hardware processor, then the device complexity is reduced, but the memory access latency increases when accessing memory locations on other processors

Engineering Contradiction:

Improveelectrical connection configurationVSAvoidmemory access latency

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The peripheral computing component is segmented into multiple independent electrical connections, each connecting to a different hardware processor. This allows the peripheral to establish direct point-to-point connections with multiple processors simultaneously, enabling fast access to memory locations on any connected processor without going through intermediate buses or controllers.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The electrical connection topology is changed from a hierarchical bus-based structure to a point-to-point dimensional structure. Each processor-memory pair has a dedicated direct connection path, transforming the access model from shared resource contention to independent parallel channels, thereby eliminating latency associated with bus arbitration and shared media.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If a peripheral computing component accesses memory locations on remote hardware processors, then the memory capacity available to the peripheral increases, but the data transfer speed decreases due to non-uniform access times

Engineering Contradiction:

Improvememory capacityVSAvoiddata transfer speed

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

The memory access path is segmented into multiple independent point-to-point connections between the peripheral computing component and different hardware processors. Each connection provides a dedicated high-speed channel, allowing the peripheral to access memory on any connected processor at local speeds rather than remote speeds.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The access time parameter is changed from non-uniform (varying based on processor distance) to uniform (consistent across all memory accesses). This is achieved by providing direct electrical connections to multiple processors, making the peripheral's access time to memory on any connected processor equivalent to accessing local memory, thereby equalizing performance across all memory locations.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If thread migration between hardware processors is enabled, then the system load balancing improves, but the network connection stability may be interrupted

Engineering Contradiction:

Improveload balancingVSAvoidnetwork connection stability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The electrical connection is segmented into multiple independent paths from the peripheral computing component to different hardware processors. When thread migration occurs, the peripheral maintains direct connections to multiple processors, allowing seamless handoff of network connections without interruption, as the migrated thread can continue using the same peripheral through its direct connection to the new processor.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The electrical connection configuration is made dynamic, allowing the system to adaptively route network connections through different processor paths based on thread location. The peripheral computing component can dynamically switch between connected processors while maintaining continuous network connectivity, enabling load balancing without compromising connection stability.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11301397B2Multiple processor computing device with configurable electrical connectivity to peripherals

Publication Date: 2022.04.12 TECHNION RES & DEV FOUND LTD

AI summary

A computing device, comprising at least one peripheral computing component, electrically connected to each of a plurality of hardware processors; wherein at least one of the plurality of hardware processors is adapted to executing a code for: configuring the at least one peripheral computing component to access at least one first memory location in a first memory component electrically coupled with a first hardware processor of the plurality of hardware processors via a first electrical connection between the peripheral computing component and the first hardware processor; and configuring the at least one peripheral computing component to access at least one second memory location in a second memory component electrically coupled with a second hardware processor of the plurality of hardware processors via a second electrical connection between the peripheral computing component and the second hardware processor; and wherein the first hardware processor is not the second hardware processor.