Multi-Processor Instruction Scheduler Balancing Workloads

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Solution Overview

Problem

Existing CPU scheduling methods fail to effectively balance workloads across processors, leading to inefficiencies due to pipeline hazards and stalls, which result in increased CPU cycles and potential computation errors.

Innovation Solution

A method that profiles processors using a cycle per instruction metric to identify unbalanced workloads and migrates instructions from a processor with a higher cycle per instruction metric to one with a lower metric, thereby rebalancing the workload and reducing pipeline stalls.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If workloads are assigned to processors without balancing, then processors may handle more instructions, but pipeline hazards and stalls increase leading to more CPU cycles and reduced efficiency

Engineering Contradiction:
Improveinstruction throughputVSAvoidCPU cycles
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent changes the workload distribution parameters by monitoring cycle per instruction metrics and dynamically reassigning instructions between processors. When a processor's CPI exceeds a threshold, the system transfers instructions to processors with lower CPI, thereby optimizing the parameter balance and reducing total CPU cycles consumed

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements a feedback mechanism where the system continuously monitors the cycle per instruction metric for each processor and uses this information to make dynamic scheduling decisions. The feedback loop identifies unbalanced workloads and triggers workload migration to maintain optimal processor performance

Inventive Principle:
Principle #23Feedback

2Reliability

If workloads are evenly distributed across processors, then pipeline stalls are reduced, but the system requires complex monitoring and dynamic reassignment mechanisms

Engineering Contradiction:
Improvecomputation accuracyVSAvoidscheduling mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent enables processors to self-regulate their workload by monitoring their own cycle per instruction metrics. Each processor effectively manages its own performance state, and the scheduling system automatically responds to performance deviations without requiring complex external control mechanisms

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10620959B2Optimized multi-processor instruction scheduler
Publication Date: 2020.04.14 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10620959B2 patent drawing
  • US10620959B2 patent drawing
  • US10620959B2 patent drawing

AI summary

In an approach for moving workloads between central processing units (CPUs) to accommodate balance, a processor profiles a first processor and a second processor of a plurality of processors, using a cycle per instruction metric. A processor assigns a first group of instructions to the first processor and a second group of instructions to the second processor. A processor sums an instruction count for the first group of instructions and an instruction count for the second group of instructions. A processor determines that a balance condition, defined by a predetermined threshold, does not exist across the first processor and the second processor. A processor identifies the second processor has a lower cycle per instruction metric than the first processor. A processor moves a workload, running on the first processor, with a maximum number of instructions of an unbalanced group to the second processor to balance workloads.