Multi-Processor Resource Management via Direct Status Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-processor systems with pipelined secondary processors, the repetitive re-transmission of acknowledgements from secondary processors to the primary processor leads to substantial delays and computational overhead, limiting performance and efficiency.
Innovation Solution
Implementing a direct access mechanism for the primary processor to status information registers in secondary processors via a dedicated data port and bus, allowing real-time access and bypassing upstream processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If acknowledgements are re-transmitted through the chain of pipelined secondary processors, then the primary processor receives task completion status, but substantial delays and computational overhead occur
Solution Approach 1:
The patent extracts the acknowledgement re-transmission function from the pipelined secondary processors. Instead of having acknowledgements propagate upstream through each processor in the chain, the system designates specific secondary processors as acknowledgement sources that can directly transmit status information to the primary processor, eliminating the need for intermediate processors to forward the same information repeatedly.
Solution Approach 2:
The patent introduces a memory-based intermediary mechanism where task status information is stored in memory locations accessible by both the secondary processors and the primary processor. This memory intermediary allows the primary processor to retrieve status information without requiring sequential re-transmission through the processor chain, thereby reducing delay while maintaining reliable status tracking.
2Loss of information
If sequential re-transmission of acknowledgements is used, then task status information is communicated upstream, but command throughput is limited
Solution Approach 1:
The patent segments the acknowledgement transmission function by allowing different secondary processors to independently transmit their own task status information directly to the primary processor. This segmentation eliminates the sequential bottleneck where only one processor could transmit at a time, enabling parallel status reporting and significantly improving command throughput while ensuring complete information communication.
3Productivity
If pipelined secondary processors are used for parallel processing, then computational efficiency is improved, but design flexibility is reduced
Solution Approach 1:
The patent introduces dynamic configurability to the pipelined processor system by allowing the primary processor to selectively access and receive status information from specific secondary processors based on task requirements. This dynamic access mechanism maintains the parallel processing efficiency of the pipelined architecture while adding design flexibility, as the system can adapt to different task allocation patterns and processor configurations without being constrained by fixed upstream communication paths.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Resource management techniques in multi-processor systems are described. Embodiments include a multi-processor system having a primary processor for communication with pipelined secondary processors. The secondary processors include registers containing status information for tasks executed by the respective secondary processors. The primary processor is provided with direct access to contents of the registers and manages computational and memory resources of the multi-processor system based on the acquired status information.