Multi-Processor Storage Device Bus Architecture
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Solution Overview
Problem
Current Flash-based storage systems face performance limitations due to single processor management over a shared bus, leading to slower data management speeds and scalability issues in robust systems, as well as limited write cycles and proprietary management requirements for Flash memory.
Innovation Solution
A distributed architecture with multiple microprocessor units, each having a dedicated bus connection to Flash configurations, allowing for independent data management and reduced RAM and bus contention, enabling faster and more reliable data access and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single processor manages Flash memory over a shared bus, then device complexity is reduced, but data management speed and scalability deteriorate
Solution Approach 1:
The patent divides the single processor into multiple microprocessor units (MPUs), each capable of independently managing Flash memory operations. This segmentation allows parallel processing of data management tasks, thereby increasing data management speed while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The patent transitions from a single-dimensional shared bus architecture to a multi-dimensional architecture where each MPU has its own dedicated bus connection to Flash configurations. This dimensional change eliminates bus contention and enables simultaneous data operations across multiple processors, significantly improving productivity.
2Productivity
If multiple microprocessor units with dedicated bus connections are used, then data management speed improves, but device complexity increases
Solution Approach 1:
The system is segmented into independent MPU modules, each with dedicated bus connections. This modular segmentation allows the complexity to be distributed and managed independently across multiple units, making the overall complex system manageable through standardized interfaces and independent operation of each segment.
3Device complexity
If a shared bus is used for processor access to Flash memory, then device complexity is reduced, but bus contention and performance bottlenecks occur
Solution Approach 1:
The shared bus is segmented into multiple dedicated buses, one for each MPU. This eliminates bus contention by providing separate communication pathways, ensuring reliable data access without the performance bottlenecks that occur when multiple processors compete for a single shared bus.
4Productivity
If Flash memory is written frequently, then data storage capacity is充分利用, but mean time before failure decreases due to limited write cycles
Solution Approach 1:
The Flash memory is divided into multiple configurations or partitions, each managed by specific MPUs. This segmentation allows for wear leveling strategies where write operations are distributed across different Flash partitions, preventing any single partition from exhausting its write cycles while maintaining high overall storage utilization.
Solution Approach 2:
The system implements wear leveling and block rotation mechanisms that discard heavily worn Flash blocks and recover them for other uses. By continuously rotating which blocks are in active use versus which are being restored, the system maintains high storage utilization while extending the overall lifespan of the Flash memory through balanced wear distribution.
Data Source
AI summary
In a system for reading and writing data, the system including a controller, multiple microprocessor units accessible to the controller, and multiple memory device configurations, each having one dedicated bus connection to individual ones or multiples of the microprocessor units, a method for managing access to one or more of the memory device configurations includes the steps, (a) receiving a request at the controller requiring access of at least one of the memory device configurations, (b) determining at the controller, which microprocessor unit or units will handle the request, (c) handing the request to the selected microprocessor unit or units, (d) determining at the microprocessor unit or units, the tasks specified in the request for that microprocessor unit or units and (e) determining a memory address or addresses in one or more of the memory device configurations and accessing the memory device configuration or configurations to satisfy the request.