Multi-Protocol Memory Access Interface for Latency Reduction
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Solution Overview
Problem
Current memory access systems face challenges in achieving low latency due to inefficiencies in communication protocols between devices and the host processor, particularly when handling data of varying sizes, which can lead to increased overhead and inefficient direct memory access operations.
Innovation Solution
A system and method that utilize multiple protocols for memory access, where a first protocol is dedicated for memory access and a second non-coherent protocol is used for input/output operations, allowing the host processor to select the optimal protocol based on data size, thereby reducing latency and enhancing system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single protocol is used for all memory access operations, then the system structure is simple, but the memory access latency increases and efficiency decreases when handling data of varying sizes
Solution Approach 1:
The system dynamically selects between first protocol and second protocol based on data size characteristics. The host processor determines whether to use the first protocol (for small data) or second protocol (for large data) in real-time, making the protocol selection adaptive rather than static. This dynamic approach reduces memory access latency for different data sizes while managing complexity through conditional logic.
Solution Approach 2:
The system changes the protocol parameter based on the data size parameter. When data size exceeds a threshold, the system switches from first protocol to second protocol. This parameter-based selection optimizes memory access efficiency by matching the protocol characteristics to the data size requirements, thereby reducing overall access latency.
2Productivity
If a dedicated first protocol is used for memory access, then memory access efficiency is improved, but the system cannot efficiently handle both small and large data transfers with a single protocol
Solution Approach 1:
The host processor is designed with multi-functionality to support both first protocol and second protocol for memory access operations. This universal capability allows the system to handle different data size scenarios efficiently - using first protocol for small data transfers and second protocol for large data transfers, thereby achieving both high efficiency and broad adaptability.
Solution Approach 2:
The system dynamically adapts its protocol selection based on the data size being transferred. The host processor evaluates the data size and switches between first protocol and second protocol accordingly, making the system versatile for different transfer scenarios while maintaining high memory access efficiency through optimal protocol selection.
3Productivity
If the host processor selects optimal protocol based on data size, then system performance is enhanced, but the control complexity increases
Solution Approach 1:
The host processor performs preliminary evaluation of data size before initiating memory access operations. By determining the appropriate protocol in advance based on data size characteristics, the system avoids runtime protocol switching complexity and makes straightforward protocol selection decisions, thereby enhancing performance without excessive control complexity.
Solution Approach 2:
The system uses a clear parameter-based decision rule where data size serves as the switching criterion. This parameter change approach simplifies the control logic - the host processor only needs to compare data size against a threshold to determine protocol selection, avoiding complex control mechanisms while still achieving optimal system performance.
Data Source
AI summary
A device configured to communicate through a bus may include a first interface circuit configured to, based on a first protocol, provide first access to a first memory through the bus and a second interface circuit configured to, based on a second protocol, provide a non-coherent input/output (I/O) interface through the bus. The second interface circuit may be configured to access the first memory in response to a message received through the bus based on the second protocol to provide second access to the first memory through the bus.