Multi-Protocol Memory Controller Architecture
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Solution Overview
Problem
Current multi-core processor architectures face limitations in memory capacity expansion due to high memory controller to processor ratios, leading to increased latency and restricted physical distance for additional memory placement, especially with solutions like multiplexed busses and fully buffered DIMMs.
Innovation Solution
A memory controller architecture that includes multiple memory channel controllers coupled to a protocol engine and system interface, allowing for configurable protocols and low power hibernation modes, enabling expansion of memory capacity with support for various DIMM technologies and protocols, and connection via multi-system interconnects like InfiniBand or Ethernet.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory controllers are integrated on die with processors to improve system density and reduce latency, then memory bandwidth scales linearly with CPU sockets, but the ratio of memory controllers to processors exceeds integration limits
Solution Approach 1:
The system is segmented into multiple independent memory controller domains, each capable of managing separate memory channels. This allows the memory controller functionality to be distributed across multiple processors or memory channel controllers, reducing the burden on any single integration point while maintaining high memory bandwidth scalability.
Solution Approach 2:
A protocol engine acts as an intermediary layer between the memory channel controllers and the processors. This mediator handles protocol conversion and memory management tasks, allowing processors to focus on computation while the protocol engine manages memory access, thereby reducing the direct memory controller to processor ratio requirement.
2Quantity of substance
If multiplexers are used to route independent memory busses into a single bus to expand memory capacity, then memory capacity can be expanded, but secondary busses must run at lower performance levels and physical distance is restricted
Solution Approach 1:
Instead of multiplexing multiple memory busses into a single shared bus, the system segments memory access into multiple independent memory channels. Each channel maintains its own dedicated bus, allowing all busses to operate at full performance levels simultaneously without the speed degradation that would result from time-multiplexed sharing.
Solution Approach 2:
The system transitions from a single-dimension shared bus architecture to a multi-dimensional parallel channel architecture. By adding the dimension of parallelism with multiple independent channels, the system achieves both expanded memory capacity and maintained high performance on all channels simultaneously.
3Quantity of substance
If fully buffered DIMMs with daisy chaining are used to expand memory capacity, then memory capacity can be expanded, but latency increases with each additional FB-DIMM
Solution Approach 1:
The memory system is segmented into multiple independent memory channels, each with its own memory controller interface. This segmentation allows simultaneous access to multiple memory modules across different channels, preventing the sequential access pattern that causes latency accumulation in daisy-chained FB-DIMM configurations.
Solution Approach 2:
The protocol engine provides universal interface capabilities that can handle multiple memory protocols and channel configurations simultaneously. This multi-functionality allows the system to optimize memory access patterns across all channels, reducing overall latency while supporting expanded memory capacity through diverse DIMM technologies.
Data Source
AI summary
A multi-protocol memory controller includes one or more memory channel controllers. Each of the memory channel controllers coupled to a single channel of DIMM, where the DIMM in each single channel operate according to a specific protocol. A protocol engine is coupled to the memory channel controllers. The protocol engine is configurable to accommodate one or more of the specific protocols. Finally, a system interface is coupled to the protocol engine and is configurable to provide electrical power and signaling appropriate for the specific protocols.