Multi-Protocol RAM Controller Using Shim Circuits
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Solution Overview
Problem
Traditional System on Chip (SoC) designs experience latency and increased contention due to the need for bus-to-bus bridges to access system memory, as each subsystem must connect through bridges that introduce unwanted delays and protocol translation, especially when using different interconnect or bus protocols.
Innovation Solution
A multi-bus protocol memory controller utilizing shim circuits to translate between various bus protocols directly to the fabric interconnect protocol, reducing the need for bridges and minimizing delay, allowing different subsystems to communicate directly with the memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If bus-to-bus bridges are used to connect subsystems to system memory, then protocol compatibility is achieved, but latency and access delay increase
Solution Approach 1:
The patent extracts the protocol translation function from traditional bus-to-bus bridges and relocates it directly into the memory controller. This allows subsystems to access memory through the memory controller's integrated protocol translation capability, eliminating the need for intermediate bridges and reducing access latency while maintaining protocol compatibility.
Solution Approach 2:
The memory controller serves as an intermediary between multiple subsystems using different bus protocols (AHB, AXI, OBI) and the system memory. By integrating multiple protocol interfaces directly into the memory controller, it mediates protocol translation without requiring external bridges, thus reducing the number of translation stages and minimizing access delay.
2Adaptability or versatility
If multiple bus-to-bus bridges are implemented for different protocols, then subsystem connectivity is enabled, but device area and power consumption increase
Solution Approach 1:
The patent merges multiple protocol interface functions (AHB, AXI, OBI) and protocol translation capabilities into a single integrated memory controller unit. This consolidation eliminates the need for separate bus-to-bus bridges for each protocol, reducing the overall device area while maintaining connectivity for multiple subsystems using different bus protocols.
Solution Approach 2:
The memory controller is designed with universal multi-functionality to support multiple bus protocols (AHB, AXI, OBI) simultaneously through integrated interfaces. This single multi-functional unit replaces multiple dedicated bridge circuits, enabling subsystem connectivity across different protocols while minimizing device area consumption.
3Productivity
If traditional RAM controllers support multiple ports, then memory access capability is improved, but protocol flexibility is limited to single protocol
Solution Approach 1:
The memory controller incorporates multiple protocol interfaces (AHB, AXI, OBI) along with multiple memory access ports. Each port can handle transactions from subsystems using different bus protocols, enabling the controller to simultaneously provide high-speed memory access capability and protocol flexibility without requiring separate controllers for each protocol.
Data Source
AI summary
A multi-bus protocol memory controller is disclosed. The memory controller utilizes shim circuits to translate between the various bus protocols used in the System on a Chip (SoC) and the bus protocol used by the memory controller. The use of shim circuits reduces the number of bridges required in the SoC and also increases performance. The memory controller is designed such that it may interface with any bus protocol, requiring only the design and inclusion of a shim circuit for that bus protocol.