Multi-Protrusion Transfer Gate for Faster Electron Transmission

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Solution Overview

Problem

Existing pixel sensors in digital cameras and optical imaging devices face challenges with electron transmission efficiency, leading to increased lag times and occurrences of photodiode saturation, particularly in deep photodiode applications.

Innovation Solution

The introduction of a transistor structure with a gate conductor featuring a plurality of conductive protrusions extending into the substrate region between doping regions, which enhances electron transmission efficiency by increasing the channel area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional gate conductor structure is used, then the device complexity is low, but the electron transmission efficiency is insufficient leading to lag times and photodiode saturation

Engineering Contradiction:
Improveelectron transmission efficiencyVSAvoidgate conductor structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate conductor is divided into multiple segments or protrusions that extend into the substrate region. This segmentation increases the effective channel area for electron transmission without requiring a complete redesign of the entire gate structure, thereby improving electron transmission efficiency while maintaining reasonable device complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate conductor structure transitions from a planar two-dimensional configuration to a three-dimensional structure with protrusions extending into the substrate. This dimensional change increases the channel area and improves electron transmission efficiency by providing additional conduction paths vertically into the substrate

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Loss of time

If the channel area is increased to improve electron transmission, then the lag time is reduced, but the device complexity increases

Engineering Contradiction:
Improvelag timeVSAvoidtransistor structure complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The channel area is increased by extending the gate conductor vertically into the substrate region, creating a three-dimensional structure. This approach reduces lag time by providing larger conduction area without proportionally increasing device complexity, as the extension utilizes the vertical dimension rather than requiring lateral expansion

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The gate conductor protrusions are nested within or extend into the substrate region, utilizing the existing vertical space. This nesting approach increases channel area for faster electron transmission while minimizing additional device complexity by integrating the structure within the existing device footprint

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration improves electron transmission efficiency, reducing lag times and occurrences of photodiode saturation, thereby enhancing the performance of pixel sensors in imaging devices.

Implementation Method 1

a gate conductor of the transistor structure includes a plurality of conductive protrusions extending into the substrate region between the first and second regions... improves electron transmission efficiency

Methodology Applied
Scientific EffectElectron conduction: Conduction (electrical)

Data Source

PatentUS12211862B2Multi-protrusion transfer gate manufacturing method
Publication Date: 2025.01.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12211862B2 patent drawing
  • US12211862B2 patent drawing
  • US12211862B2 patent drawing

AI summary

A method of manufacturing a transistor structure includes forming a plurality of trenches in a substrate, lining the plurality of trenches with a dielectric material, forming first and second substrate regions at opposite sides of the plurality of trenches, and filling the plurality of trenches with a conductive material. The plurality of trenches includes first and second trenches aligned between the first and second substrate regions, and filling the plurality of trenches with the conductive material includes the conductive material extending continuously between the first and second trenches.