Multi-Pulse Memory Cell Selection Preventing Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory devices face challenges in selecting all desired memory cells during read or write operations, leading to higher error rates due to current leakage and insufficient voltage distribution across word lines.
Innovation Solution
A memory device implements a multi-pulse selection procedure, applying a first voltage pulse to a selected bit line while maintaining deselected word lines at a constant voltage, followed by a second and third pulse with varying voltages to prevent current leakage and ensure targeted memory cell selection, using a cross-point architecture with chalcogenide materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single voltage pulse is applied to select memory cells, then the selection process is simple and fast, but current leakage occurs and not all desired memory cells can be reliably selected
Solution Approach 1:
The selection procedure is divided into multiple discrete voltage pulse stages (first pulse, second pulse, third pulse) with different voltage levels and timing characteristics. Each pulse serves a specific function in the selection process, allowing reliable selection of all desired memory cells while preventing current leakage through systematic segmentation of the selection operation.
Solution Approach 2:
The selection process uses periodic voltage pulses applied at specific time intervals. The first pulse is applied during a first time period, the second pulse during a second time period, and the third pulse during a third time period. This periodic action with controlled timing ensures that memory cells are selected reliably without causing current leakage, as each pulse occurs at an optimal moment in the selection sequence.
2Reliability
If voltage is applied to all word lines simultaneously, then all memory cells receive sufficient voltage, but current leakage increases and power consumption rises
Solution Approach 1:
The first voltage pulse is applied in advance to deselected word lines before the main selection pulse is applied to the selected word line. This preliminary action pre-charges or pre-discharges the capacitance of deselected word lines, preventing current leakage when the selected word line receives the main pulse. By performing this action beforehand, the system ensures reliable memory cell selection while minimizing energy loss.
Solution Approach 2:
The system dynamically adjusts voltage levels applied to different word lines at different times. Deselected word lines receive a first voltage level during the first time period, while the selected word line receives a higher second voltage level during the second time period. This dynamic voltage adjustment ensures that each memory cell receives the appropriate voltage for reliable selection while preventing current leakage through properly timed voltage application.
Data Source
AI summary
Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected.