Multi-Queue Single-FIFO Architecture for QoS Systems
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Solution Overview
Problem
Conventional communication systems with multiple queues rely on numerous first-in-first-out (FIFO) buffers, leading to increased IC chip size, cost, and power consumption, necessitating a reduction in the number of FIFO buffers for improved cost effectiveness.
Innovation Solution
A multi-queue single-FIFO architecture is implemented, where an arbiter determines the next queue to service based on quality of service (QoS) policies, using a single FIFO buffer or two buffers in parallel to manage data packets, reducing the overall number of FIFO buffers required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple FIFO buffers are used to service multiple queues, then QoS guarantees can be maintained, but IC chip size increases
Solution Approach 1:
The patent merges multiple FIFO buffer functions into a single shared FIFO buffer that services multiple queues. Instead of having separate FIFO buffers for each queue, the system uses one common FIFO buffer with a pointer mechanism to track which queue should be served next, thereby reducing the total number of FIFO buffers while maintaining QoS guarantees.
Solution Approach 2:
The single FIFO buffer is designed to serve multiple queues universally. The arbiter component determines which queue should be serviced next based on QoS policies, and the same FIFO buffer handles data packets from any of the multiple queues, making the FIFO buffer a multi-functional component rather than dedicated to a single queue.
2Reliability
If multiple FIFO buffers are used to service multiple queues, then QoS guarantees can be maintained, but power consumption increases
Solution Approach 1:
The patent merges multiple FIFO buffer functions into a single shared FIFO buffer that services multiple queues. Instead of having separate FIFO buffers for each queue, the system uses one common FIFO buffer with a pointer mechanism to track which queue should be served next, thereby reducing the total number of FIFO buffers while maintaining QoS guarantees.
3Productivity
If multiple FIFO buffers are used to service multiple queues, then data packet management can be ensured, but system cost increases
Solution Approach 1:
The patent merges multiple FIFO buffer functions into a single shared FIFO buffer that services multiple queues. Instead of having separate FIFO buffers for each queue, the system uses one common FIFO buffer with a pointer mechanism to track which queue should be served next, thereby reducing the total number of FIFO buffers while maintaining QoS guarantees.
Data Source
AI summary
A multi-queue single-FIFO scheme for quality of service oriented communication. According to the invention, an arbiter maintains a number of next access pointers for multiple queues storing data packets to be transmitted. The arbiter also determines which queue is to be serviced next contingent upon a quality of service policy and then fetches at least one data packet, identified by the chosen queue's next access pointer, through a peripheral bus by means of direct memory access (DMA). A single FIFO buffer is connected to the arbiter to store and manage the fetched data packet in a first-in-first-out manner. Following the FIFO buffer, physical layer interface logic accepts each data packet, if available, and prepares the data packet for transmission on a physical medium.