Reconfigurable Multi-Radix FFT Circuit for Variable Transform Sizes
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Solution Overview
Problem
Existing digital signal processing systems face challenges in efficiently performing discrete Fourier transforms (DFT) and Fast Fourier transforms (FFT) of varying sizes, particularly in high-data-rate applications like 5G networks, where large data sets require efficient computation without dedicated hardware for each transform size.
Innovation Solution
A reconfigurable digital logic circuit with multimode radix processing chains, a radix-P engine, and a memory system that can perform DFT/FFT of any size 2k and DFT of any size 2a*3b*5c, utilizing a multi-radix DFT circuit supporting radix-3, radix-4, and radix-5 computations, and a memory system to handle variable data sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dedicated hardware is designed for each transform size to achieve high computation speed, then computation speed is improved, but device complexity and hardware requirements increase
Solution Approach 1:
The patent implements a universal DFT/FFT circuit that can perform transforms of multiple sizes (N=2^k and N=2^a*3^b*5^c) using the same hardware architecture. The circuit uses reconfigurable processing chains and routing switches to adapt to different transform sizes, eliminating the need for dedicated hardware for each size while maintaining high computation speed through optimized signal flow paths.
Solution Approach 2:
The circuit employs dynamic reconfiguration capabilities where processing chains, routing switches, and data flow paths can be dynamically adjusted based on the required transform size. This allows the same hardware to optimize its structure for different computation tasks, achieving high speed for various transform sizes without requiring separate dedicated circuits for each configuration.
2Speed
If a fixed-size DFT/FFT circuit is designed to achieve fast computation, then computation speed is improved, but adaptability to different transform sizes deteriorates
Solution Approach 1:
The circuit is designed as a universal processor that can handle transform sizes of N=2^k and N=2^a*3^b*5^c using the same hardware. Multiple processing chains with reconfigurable routing allow the circuit to adapt to different transform sizes while maintaining optimized signal paths for fast computation, thus achieving both speed and versatility.
Solution Approach 2:
The DFT/FFT computation is divided into multiple processing chains that can be independently configured. Each chain processes a portion of the transform, and the number/activation of chains can be adjusted based on the required transform size. This segmentation allows the circuit to maintain high computation speed for the active chains while adapting to different overall transform sizes.
3Productivity
If multiple dedicated circuits are provided for different transform sizes to support high data rates, then productivity is improved, but device complexity increases
Solution Approach 1:
A single universal DFT/FFT circuit processes multiple transform sizes (N=2^k and N=2^a*3^b*5^c) through reconfigurable processing chains and routing switches. This eliminates the need for multiple dedicated circuits while maintaining high data processing capability for 5G networks and other high-data-rate applications, thus improving productivity without increasing device complexity.
Solution Approach 2:
The patent merges multiple transform size capabilities into a single integrated circuit architecture. By combining multiple processing chains, routing switches, and control logic into one unified structure, the circuit achieves the functional equivalent of multiple dedicated circuits while reducing overall device complexity and hardware resource requirements.
Data Source
AI summary
Reconfigurable digital logic circuits and methods of operation can be used to accelerate computation of Fast Fourier Transforms (FFT) and discrete Fourier transforms (DFT) for a range of sizes. In some embodiments, the same circuit can be reconfigurable to support FFT of any size 2k (for positive integer k) and DFT for of any size 2a*3b*5c for non-negative integers a, b, c.